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Welcome to Hierarchic al Design - Design Preservati on and Partial Reconfigur ation
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06-29-2010 01:50 PM - edited 07-27-2010 09:07 AM
Welcome to the Xilinx Hierarchical Design Forum. This is the forum for all of your Design Preservation and Partial Reconfiguration questions.
The major goal of Design Preservation is to reduce the number of synthesis and implementation iterations during the timing closure phase. This is accomplished by using previous implementation results for unchanged portions of the design.
The major goal of Partial Reconfiguration is to allow a portion of the design to be reconfigured while the rest of the design is still running in the FPGA. Different configurations of the design can be swapped back and forth reducing overall design size and power.
For more information on the Design Preservation flow please see:
White Paper - Repeatable Results with Design Preservation
Hierarchical Design Methodology Guide
PlanAhead_Tutorial_Design_Preservation
Leveraging Design Preservation for Predictable Results Video
For more information on the Partial Reconfiguration flow please see:
Partial Reconfiguration Website
Partial Reconfiguration User Guide
Partial Reconfigurations using PlanAhead Video
This forum is monitored by several Xilinx employees. Please feel free to ask any questions.
Re: Welcome to Hierarchic al Design - Design Preservati on and Partial Reconfigur ation
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12-21-2010 12:28 PM - edited 12-21-2010 12:45 PM
hi
DId you mean the design based in partition???
Re: Welcome to Hierarchic al Design - Design Preservati on and Partial Reconfigur ation
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12-21-2010 12:43 PM
hi
I you helpful link: !!!
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Re: Welcome to Hierarchic al Design - Design Preservati on and Partial Reconfigur ation
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01-09-2011 06:22 PM
Hi,
I need to certain partitions out of certain area in my design.
I have modularized my design into the parts that I want to separate from eachother.
I think I'll have to use the partition method. Are there any examples on the command flow method?
If I understand correctly, the command-flow method works as so:
Generate .ngc files for each VHDL component by making ISE projects for each component.
2.Write an xparameter.pxml to explain to the tool what the hierarchy is.
Make a UCF that declares the regions as CLOSED group and CLOSED place.
Run NGDbuild with all the ngc's (generated in step 1) as input files.
Run map and PAR the same way as in 4
Is this right or did I get this completely wrong? Again, are there any examples? I do NOT want to use a GUI.
Thank you,
Sudhanshu
Re: Welcome to Hierarchic al Design - Design Preservati on and Partial Reconfigur ation
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01-09-2011 10:16 PM
To everyone: do not post your questions in this thread!
Open a new thread for your question (the "New Message" button here).
Signature:
1. Google your question before asking it.
2. If Google doesn't find a solution, post your question in a detailed, comprehensive, and clear way.
3. If someone answers your question, mark the post with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left).











