05-08-2012 02:29 PM
In ML605 board, I try to implement a simple degin with GTX_X0Y17 and the reference clock is Q4_MGTREFCLK, 1 signals are not completely routed when i routed. I don't know why and how to solve this problem.
Here is the instance:
IBUFDS_GTXE1 q4_clk1_refclk_ibufds_i (
.I (RX_REF_CLK_P), // Connect to package pin F6( H6 is assiged)
.IB (RX_REF_CLK_N) // Connect to package pin F5 (H5 is assigned)
Release 13.4 - par O.87xd (nt64) Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Tue May 08 17:22:34 2012
1 signals are not completely routed.
WARNING:ParHelpers:360 - Design is not completely routed.
05-08-2012 07:32 PM
Examine the partially routed design in FPGA Editor and examine the net. You can easily find the unrouted net by setting the list window to "unrouted nets". If you can't figure out what's wrong post a screenshot of the highlighted net and a pin list.