Implementation

[rex_nyu]

Hi all,

I have 8 2-to-1 muxes which share the same select signal. On a Virtex-5 110T device, I am able to map these muxes into one single slice.

E.g.

module mux_8(a, b, sel, o);
input [7:0] a;
input [7:0] b;
input sel;
output [7:0] o;

mux mux_0(.a(a[0]), .b(b[0]), .sel(sel), .o(o[0]));
mux mux_1(.a(a[1]), .b(b[1]), .sel(sel), .o(o[1]));
mux mux_2(.a(a[2]), .b(b[2]), .sel(sel), .o(o[2]));
mux mux_3(.a(a[3]), .b(b[3]), .sel(sel), .o(o[3]));
mux mux_4(.a(a[4]), .b(b[4]), .sel(sel), .o(o[4]));
mux mux_5(.a(a[5]), .b(b[5]), .sel(sel), .o(o[5]));
mux mux_6(.a(a[6]), .b(b[6]), .sel(sel), .o(o[6]));
mux mux_7(.a(a[7]), .b(b[7]), .sel(sel), .o(o[7]));

endmodule

(* LUT_MAP = "yes" *)
(* RLOC = "X0Y0" *)
module mux(a, b, sel, o);
input a;
input b;
input sel;
output o;

assign o = (~sel & a) | (sel & b);
endmodule

However, if I increase the number of 2-to-1 muxes to 16 and they still share the same select signal. Xilinx map all these 16 muxes to 3 slices instead of 2 slices. The code is below:

module mux_128(a, b, sel, o);
input [15:0] a;
input [15:0] b;
input sel;
output [15:0] o;

(* RLOC = "X0Y0" *) mux mux_0(.a(a[0]), .b(b[0]), .sel(sel), .o(o[0]));
(* RLOC = "X0Y0" *) mux mux_1(.a(a[1]), .b(b[1]), .sel(sel), .o(o[1]));
(* RLOC = "X0Y0" *) mux mux_2(.a(a[2]), .b(b[2]), .sel(sel), .o(o[2]));
(* RLOC = "X0Y0" *) mux mux_3(.a(a[3]), .b(b[3]), .sel(sel), .o(o[3]));
(* RLOC = "X0Y0" *) mux mux_4(.a(a[4]), .b(b[4]), .sel(sel), .o(o[4]));
(* RLOC = "X0Y0" *) mux mux_5(.a(a[5]), .b(b[5]), .sel(sel), .o(o[5]));
(* RLOC = "X0Y0" *) mux mux_6(.a(a[6]), .b(b[6]), .sel(sel), .o(o[6]));
(* RLOC = "X0Y0" *) mux mux_7(.a(a[7]), .b(b[7]), .sel(sel), .o(o[7]));

(* RLOC = "X0Y1" *) mux mux_8 (.a(a[8]),  .b(b[8]), .sel(sel),  .o(o[8]));
(* RLOC = "X0Y1" *) mux mux_9 (.a(a[9]),  .b(b[9]), .sel(sel),  .o(o[9]));
(* RLOC = "X0Y1" *) mux mux_10(.a(a[10]), .b(b[10]), .sel(sel), .o(o[10]));
(* RLOC = "X0Y1" *) mux mux_11(.a(a[11]), .b(b[11]), .sel(sel), .o(o[11]));
(* RLOC = "X0Y1" *) mux mux_12(.a(a[12]), .b(b[12]), .sel(sel), .o(o[12]));
(* RLOC = "X0Y1" *) mux mux_13(.a(a[13]), .b(b[13]), .sel(sel), .o(o[13]));
(* RLOC = "X0Y1" *) mux mux_14(.a(a[14]), .b(b[14]), .sel(sel), .o(o[14]));
(* RLOC = "X0Y1" *) mux mux_15(.a(a[15]), .b(b[15]), .sel(sel), .o(o[15]));
endmodule

(* LUT_MAP = "yes" *)
module mux(a, b, sel, o);
input a;
input b;
input sel;
output o;

assign o = (~sel & a) | (sel & b);
endmodule

If I increase the the number of muxes to 24, then Xilinx will map to 4 slices.

What is the reason for this?

[austin]

r,

Synthesize it, and place and route it..  Then create a bitstream.  Look at the resultant file in FPGA_Editor.

[rex_nyu]

Hi Austin,

I take a look at the layout in the FPGA editor.

If I have 8 muxes, all of them are map to a single slice.

If I have 16 muxes, then all of them map to two slices, except one mux maps to a third slice.

If I have 24 muxes, then all of them map to three slices, except one mux maps to a fourth slice.

From the layout, I still dont quite understand why the last mux maps to an extra slice.

Could you please give some hints?

[austin]

r,

The tools have no reason to pack anything in an "optimal"  fashion, unless there are constraiints to do so.

The tools rather take whatever space is available, reserving some room, so interconnection is not blocked, and congestion is avoided.

In general, one may always pack logic more optimally by hand, but at some point (very early) designs grow too big to be handled by hand.

"Optimal" is only defined as "did it meet all constraints" and "does it work?"  How you feel about it, does not have anything to do with it.  Usage or "fulness" in the FPGA view, does not tell the whole story.

In the very first days of designing with FPGA devices (when they were invented by Xilinx, the 2016, and 2064) I knew of a few designs that were done entirely by hand, using FPFA Editor (!).

Placing and routing is a complex process, and people are always looking for better algorithms.

[rex_nyu]

I understand the complexity of you mention and I apologize for not mentioning my design goal. So here is the story:

My design is as simple 16 muxes as I said. Therefore, I can afford playing with the design by hand (I know this is quite an artificial design). My only concern is to reduce slice utilization and I try to use RLOC to constraint the place and route instead of letting the CAD tool to do it.

My question is so simple. Even if I explicitly let the tool know I want to use 2 slices, it still give me 3 slices while the second slice still have space to pack one more mux. Why? Sure, there might be some place and route violations, but I want to know which one I violated. (There is no error or warning messages) Could you be specific?

[austin · Accepted solution]

r,

Try to route it by hand, all in one slice.  You will either be able to do it (and then you can lock it down, and use it as a fixed template for that function), or you will find you run out of something, and can not do it.

When you run out of something, then you will know why.

I have no idea what resource it is that is not available.  It could be a route to get in, or out.  If there are no period constarints (any delay is acceptable), then I agree with you, it should be possible to do (but I would not expect the tools to do it, regardless).

[rex_nyu]

Yes. That is a good suggestion. Routing the design by hand should give me the answer and I will try the library instantiation approach too. 

Thank you!

[rex_nyu]

I have tried the library instantiation approach. The CAD tool is smart enough for create different h_set for the RLOC instantiation and it gives me the expected slice utilization.

Many thanks!