01-06-2011 06:20 AM
I have created a top level vhdl module which includes multiple compnents and I would like to use and area constraint for each of these components individually.
I cannot do this when I have the keep_hierarchy attribute set to "no" so I have to set it to "yes" which then leads to the entire design using more resources than I would like.
I would like the top level design to keep hierarchy so that I can contrain the components but for the next level, I dont want to these components to keep the hierarchy. I have tried to set the keep_hierarchy attribute to "yes" in the top level module and then to "no" in the vhdl for the second level but the top level keep_hierarchy attribute seems to override this and propagates through the design.
Is there a way to overcome this?
Solved! Go to Solution.
01-06-2011 08:02 AM
What synthesis tool are you using? Have you tried more than one synthesis tool?
I find these sorts of results and issues highly dependent on the tool, and trying to enforce your idea of what is best is useless: the tool vendor has made (most) of the choices for you: you don't get the freedom you think.
Why do you need to do what you are trying to do? It has been posted before that an area constraint may have worse overall results than a good speed constraint, for example. Have you tried other constarints instead of area? Have you used PlanAhead to constrain each block of code to a specific fixed size region (one way to do what you want)?
In a poerfect world, what you are trying to do would work. But, that would be your own personal world, and I am afraid we can not join you there.
Xilinx San Jose
01-11-2011 08:57 AM
Thanks for the replies. I have managed to solve the problem.
I had already tried using the ucf constraint but that was overwritten by the top level property.
By setting the top level keep_hierarchy to "no" and the next level to "yes" in the vhdl. I was able to constrain each module into an individual area group. It seems that I may not have grasped the concept properly in my mind. By setting the top level keep_hierarchy to "no", it was my understanding that each of the modules I had created would not be maintained as described in the vhdl, but it seems this is not the case.
Thanks for help
05-24-2012 12:37 PM
Austin said everything except an answer.
BTW I did not find attribute inheritance ruls anywhere in manuals!
Do sub-modules inherit all attributes of parent?
Do they do the same if constraints are passed thrue UCF?
Thank you all.
05-24-2012 01:50 PM
I wouldn't use keep hierarchy to do this since it's possible to close area groups to outside pack and placement anyway with GROUP=CLOSED and PLACE=CLOSED.
INST "module_name/*" AREA_GROUP="AG_module_name";
AREA_GROUP "AG_module_name" RANGE=SLICE_X0Y0:SLICE_X100Y100;
AREA_GROUP "AG_module_name" GROUP=CLOSED;
AREA_GROUP "AG_module_name" PLACE=CLOSED;
You don't have to define a range. If all you're interested in doing is blocking the outside packs, use just GROUP=CLOSED.
05-25-2012 01:38 AM
Bwade thank you for this strategic point.
Please clarify for me: if I use partitioning from command line
will GROUP be enough to let MAP see the corresponding module?
Now I do keep_hierarchy to let MAP see it.