Implementation

[garengllc]

I am still learning some of the innerworkings of FPGA designing and I have a design I inheirited that makes it through the mapping stage in a very reasonable few minutes, but then it chugs on the PAR stage for about 40 minutes (I know that that is crazy fast compared to some people's designs), but I would like to know if there are any best practices I can do to speed things up.  That step used to take only a few minutes, but we've recently implimented some timing constraints on some clocks due to timing errors we were seeing and now I am getting the huge PAR delay (though the timing errors seems to be fixed).

Obviously I can't do much about the timing constriants since they seem to be necessary (so I may be stuck), but is there anything else I can do on my end to help speed up the process?  I've heard rumblings of potentially using a "design guide," but I can't really find any information on that.

Thanks.

[eilert]

Hi,

you probably mean a "guide design".

That is a PAR result of a former run.

It can the be used by another implementation run of the same design as a starting point for further improvements.

Another keyword for this approach is SmartGuide Technology. You find details about this in the ISE documentation.

Have a nice synthesis

  Eilert

[rcingham]

Also, more recent verions of PAR can use up to 4 cores in parallel for some parts of the run, so make sure you enable this.

[garengllc]

I had previosuly checked to make sure I was multi-core enabled, so I know I am OK there.

I will checkout the guide design and smartguide and see what I can come up with.

Thanks!

[garengllc]

Well I implemented it (an easy enough process), but it didn't seem to help any.  I guess the timing constraints in the ucf must just make it too difficult to get around.

Thanks for pointing me in the right direction though.

[bassman59]

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garengllc wrote:

Well I implemented it (an easy enough process), but it didn't seem to help any.  I guess the timing constraints in the ucf must just make it too difficult to get around.

Thanks for pointing me in the right direction though.

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The timing constraints should be set to what's actually required by the design. There is no benefit to specifying a 100 MHz oscillator for your board and then constraining the design to run at 150 MHz.

Of course, if your design must run at 100 MHz and it doesn't meet timing, then you've got other issues.