1. whether synthesis/MAP/P&R process will automatically insert buffers for the clock signals.
I thought this is a synthesis property selection, but I cannot find it. If you explicitly instantiate the clock buffers, this question becomes moot.
Also, see the BUFFER_TYPE attribute description in UG627.
2. What if i am using DCM to generate some clock(eg. x4, x1_180,x4_180 etc) will i have to buffer these outputs from DCM before using them.
Yes. This applies to PLL outputs and clock inputs as well as DCM outputs. Clock buffers provide both drive and low-skew interconnect.
3. if i have a derived clock in my user logic (eg %2,%4) using counters shall i buffer them
If the signal is used as a clock, and clock distribution skew must be minimised, then the answer is yes.
4. For forwarding one of the internal clocks to an external pin(say for operaing an SDR) what is the best method.And how do i constrain such outputs which are driven by a derived clock not from an external clock.
This is a frequently asked (and answered) question. From the New Users Forum README thread:
clock forwarding to an output pin link#1 link#2
The linked threads refer specifically to Spartan-6 devices, but the details are almost entirely the same for other device families.
-- Bob Elkind
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README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369
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