10-22-2010 11:24 PM - last edited on 05-02-2012 05:45 AM by peadard
10-26-2010 06:30 AM
There is no difference in reality. You can use FPGA editor to manually route a design, no one does this any more but it used to be the way to route designs a long time ago.
Once you have a route, you can use FPGA editor to generate DIRT (directed routing) strings. These are entered at the UCF stage and guarantee your routing. They are relative, so one lock can be used in similar locations in the design. You also need to lock the logic that is connected to the design. This requires a specific lock constraint, if that is on a lut then that may change during synthesis which creates a problem for the constraint.
Generally you should only use DIRT strings when you have a critical tight timing requirement to hit. When it comes to closing timing, focus on reducing logic layers via your HDL. This will fix 99% of your timing issues. You could also try the partition flow to fix routing.
10-26-2010 06:55 AM
The DIRT constraint will regenerate the same routing on subsequent revisions of the design. Just locking the routing has no effect on future revisions.
04-25-2012 11:33 AM
I am applying DIRT to a section of a design which is kept unchanged in a revision of the HDL. The moment I try to run Translate (after resynthesizing) with the UCF including DIRT, a lot of errors not finding INSTANCES (LUTs & FFs) appear. If I comment the missing locks, results are not as expected.
Is there any way to tell the synthesizer to keep the INSTANCES from one run to another (with a slightly modified design)?
Thank you for your support