How can I change the default parameters for timing design in the Fpga editor?

agump · ‎05-12-2011

I search the mannual ant It says that I can use command 'setattr' to set voltage or temperature. I follow this and make sure that the command success with command 'getattr main' . But I find that the Fpga Editor reports the same net delay at different voltage and temperature. It puzzles me. What effects have the command 'setattr main voltage' and the command 'setattr main temperature'? Hope for your help .Thanks.

rcingham · ‎09-09-2010

What version of tools?

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"If it don't work in simulation, it won't work on the board."

agump · ‎05-12-2011

I am using 12.4 and the platform is win32.

brucey · ‎03-24-2010

Fpga Editor will get back the max delay of nets.
You can try Timing Analyzer instead.

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How can I change the default parameters for timing design in the Fpga editor?

Re: How can I change the default parameters for timing design in the Fpga editor?

Re: How can I change the default parameters for timing design in the Fpga editor?

Re: How can I change the default parameters for timing design in the Fpga editor?