Implementation

[akozak]

Hello,

  I am using a Virtex-5FX130T with ISE12.4 and I am having problems meeting timing constraints between two clock domains.  I have tried adding a TIG between the two clocks but I receive a warning during translate stating that the constraints were not derived:

WARNING:ConstraintSystem - TNM : ADC_CLK_GRP was distributed to a DCM but new
   TNM constraints were not derived. The requirement for derived TNM constraints
   is that the distributed TNM is referenced by no more than a single PERIOD
   constraint. Non-PERIOD referencers are also not allowed. This TNM is used in
   the following user groups or specifications:

I have a differential clock that I use as the input to the IBUFGDS.  The output of the IBUFGDS is then used as an input to a dcm that divides the clock by 2 and outputs the new halved clock into its 0 and 180 phase (this clock is being used to read an ADC at DDR). 

The TIGs are being ignored.

How can I resolve this problem?

Thank you

[graces]

When a TNM_NET property is traced into the CLKIN pin of a DLL, DCM, PLL, or MMCM, the TNM group and its usage are examined. The TNM is pushed through the CLKDLL, DCM, PLL, or MMCM (as described below) only if the following
conditions are met:
• The TNM group is used in exactly one PERIOD specification.
• The TNM group is not used in any FROM-TO or OFFSET specifications.
• The TNM group is not referenced in any user group definition.
If any of the above conditions are not met, the TNM is not be pushed through the CLKDLL/DCM/PLL/MMCM, and a warning message is issued.

So the complete warning message (from translate report) would show you which other user groups or specifications the TNM is used.

I suppose probably the TNM is used in one group involved in the TIG constraint.

If this is the case, the resolution is to create two TNM Groups for your input clock. One used for the FROM-TO-TIG constraint and the other for the PERIOD propagation.

Please have a look at this answer.

www.xilinx.com/support/answers/37782.htm

[rcingham]

Really not sure whether this is relevant to OP's problem, but the thread isn't marked as 'Solved', and it might help someone who finds this thread in a search...

Virtex-4; ISE 10.1

With an instantiated IBUFGDS feeding DCM(s), the period constraint on the input clock was not being forwarded through to the output of the DCMs.

When I changed to separate IBUFDS and BUFG with an explicitly named signal between them, it was.

[bassman59]

---

rcingham wrote:

Really not sure whether this is relevant to OP's problem, but the thread isn't marked as 'Solved', and it might help someone who finds this thread in a search...

Virtex-4; ISE 10.1

With an instantiated IBUFGDS feeding DCM(s), the period constraint on the input clock was not being forwarded through to the output of the DCMs.

When I changed to separate IBUFDS and BUFG with an explicitly named signal between them, it was.

---

My experience with V4 (and S3) is that when you use a DCM, you have to instantiate all buffers all the time.

[akozak]

By creating a new TNM_NET the following message is received:

WARNING:ConstraintSystem - TNM : ADC_CLK_GRP was distributed to a DCM but new
   TNM constraints were not derived. This TNM is used in the following user groups or specifications:

So it is not resolved.  I still need a TIG between the ADC_CLK and its outputs from the dcm that divides the clock in half and spits out the two phases.

[akozak]

The solution might be to use the DCM before the IDDR and then use an IDDR_2CLK.

Will post again if this is the solution