Implementation

[chevalier]

Hello all,

I'm trying to implement a design using the GTX (Aurora 8b10b core). Eveything is fine except that the MGTREFCLKP/N nets are not connected to the pads. The design implements completely, but map reports the following:

WARNING:MapLib:701 - Signal MGT_CLOCK_P_F6 connected to top level port MGT_CLOCK_P_F6 has been removed.

WARNING:MapLib:701 - Signal MGT_CLOCK_N_F5 connected to top level port MGT_CLOCK_N_F5 has been removed.

These are the two MGTREFCLKP/N pins that I need to clock the GTX from the outside world. Looking into the FPGA Editor (post place & route) gets the attached image. The red net is the MGT_CLOCK net that routes to the GTXE1 tile. The problem is that the inputs of the IBUFDS_GTXE1 are not connected to the pad just left to it. Why is that?

I trace down all my code and can't see why these are unconnected.

The top-level VHDL entity contains the following:

    -- MGT signals

    MGT_CLOCK_P_F6: in STD_LOGIC;

    MGT_CLOCK_N_F5: in STD_LOGIC;

    MGT_TX_P_B1: out STD_LOGIC;

    MGT_TX_N_B2: out STD_LOGIC;

    MGT_RX_P_D5: in STD_LOGIC;

    MGT_RX_N_D6: in STD_LOGIC;

The tiop-level VHDL architecture contains the following:

  PIN_F6_F5: IBUFDS_GTXE1

    port map (

      I => MGT_CLOCK_P_F6,

      IB => MGT_CLOCK_N_F5,

      CEB => '0',

      O => MGT_CLOCK,

      ODIV2 => open

    );

and all the MGT_CLOCK signals is routed to the GTXE1_X0Y18 tile through the Aurora 8b10b core. By the way, all other GTXE1 dedicated pins (ie TXP/N and RXP/N) are connected properly.

The UCF contains the following:

INST "PIN_F6_F5" LOC = IBUFDS_GTXE1_X0Y9;

INST "U3/U5/U4/gtx_wrapper_i/GTXE1_INST/gtxe1_i" LOC = GTXE1_X0Y18;

NET "MGT_CLOCK_P_F6" LOC = "F6";

NET "MGT_CLOCK_N_F5" LOC = "F5";

NET "MGT_TX_P_B1" LOC = "B1";

NET "MGT_TX_N_B2" LOC = "B2";

NET "MGT_RX_P_D5" LOC = "D5";

NET "MGT_RX_N_D6" LOC = "D6";

Any idea?

Thanks!

Claude

[kka]

Can you specify the device and package?

[chevalier]

Hi,

I'm using the Xilinx ML605 board. The part is the XC6VLX240T-1FF1156C. I'm using ISE 13.3 on Win 7.

Claude

[rcingham]

On Virtex-5, we have the ref ports defined on the top-level entity, and assign a LOC constraint to them (in the UCF). Because the Aurora IP we are using needs the RefClk as an input we connect them through to that via a IBUFDS. So, pretty much what you did...

[chevalier]

I finally instantiated IBUF on pins F5 and F6, and routed both outputs to the input of the IBUFDS_GTXE1. It worked. Everything is connected as shown in the first two lines of the attached file.

This said, even though that's what I coded, I don't really think I ended up with two IBUF in front of the IBUFDS_GTXE1. I think that's what the IPAD designation (attached file) means... meaning that an IPAD is just a pad with no buffer, as opposed to the designation IOB. The other thing is that even though we are talking of a differential MGT CLOCK signal, the pads are treated as two single-ended connections until they reach the inputs of the IBUFDS_GTXE1. That's really weird and counter intuitive. And by the way, it's exactly the same for TXP/N and RXP/N that are also input and output individually as single-ended signals using 2 IBUF (RX) and two OBUF (TX).

The MGT being a hardware core, I would have expected its IOs to be automatically connected as soon as the GTXE1 tile is instantiated and located...

At the end, I guess the question is how am I supposed to know how to connect things other than trial an error? Is this documented somewhere? And this is true for other cores as well (eg EDK axi_v6_ddrx)... not only Aurora.

Claude