It looks like you wrote some code of your own to do an SDR SDRAM interface?
Some tips:
If you code with VHDL and you need feedback from a register that goes to a pin,
DON'T make it an INOUT or BUFFER port. Make it an output and use an internal
register signal for the feedback. This will allow the tools to replicate the register
(one for the feedback, one for the IOB) rather than forcing feedback from the pin
or use of a single register driving both OBUF and internal loads. Make sure
you enable register duplication to allow the register to be packed into the IOB.
Same goes for Verilog, use an output port, not an inout. You don't need to define
an internal variable in Verilog for feedback, however.
If you think there should not be this problem (don't see where the internal loads are),
you can change the "FORCE" to "TRUE" to demote these errors to warnings. Then
you can look at the technology schematic or open the design in FPGA editor to
see where these signals go.
HTH,
Gabor
-- Gabor
