PART: xc6vsx475tff1759-1
Tools: Synplify Pro E-2010.09-SP2
ISE 13.3
There's a BRAM utilization mismatch in my design. I use Synplify Pro to generate the netlist. The BRAM utilization shown by Synplify Pro is 78%. When I run that netlist through ISE, I get a BRAM over-mapped error (128%). What could be the cause of this mismatch?
Here's Synplify's resource usage report (.srr file):
---------------------------------------
Resource Usage Report for ws6vpxcpe
Mapping to part: xc6vsx475tff1759-1
Cell usage:
BUF 3 uses
BUFIO 32 uses
DSP48E1 337 uses
FD 55673 uses
FDC 12259 uses
FDCE 12847 uses
FDC_1 20 uses
FDE 113031 uses
FDP 653 uses
FDPE 889 uses
FDP_1 18 uses
FDR 19891 uses
FDRE 44693 uses
FDS 842 uses
FDSE 753 uses
GND 5894 uses
IBUFDS_GTXE1 8 uses
IDELAY 4 uses
IDELAYCTRL 1 use
IODELAY 72 uses
IODELAYE1 262 uses
LD 4 uses
MMCM_BASE 4 uses
MULT_AND 1 use
MUXCY 516 uses
MUXCY_L 2649 uses
MUXF7 4667 uses
MUXF8 1918 uses
RAM128X1D 48 uses
RAM64M 7710 uses
RAM64X1D 330 uses
RAMB16 1304 uses
RAMB18E1 223 uses
RAMB36E1 69 uses
ROC 1 use
VCC 5894 uses
XORCY 2842 uses
LUT1 3271 uses
LUT2 37788 uses
LUT3 32096 uses
LUT4 10830 uses
LUT5 13317 uses
LUT6 21678 uses
LUT6_2 52 uses
I/O ports: 987
I/O primitives: 1357
IBUF 18 uses
IBUFDS 80 uses
IBUFG 2 uses
IBUFGDS 2 uses
IDDR 10 uses
IOBUF 201 uses
IOBUFDS 24 uses
ISERDESE1 200 uses
OBUF 162 uses
OBUFDS 80 uses
OBUFT 232 uses
ODDR 20 uses
OSERDES 326 uses
BUFG 12 uses
BUFGCE 3 uses
SRL primitives:
SRLC32E 1 use
SRL16E 2102 uses
I/O Register bits: 0
Register bits not including I/Os: 152827 (25%)
Latch bits not including I/Os: 4 (0%)
RAM/ROM usage summary
Dual Port Rams (RAM16X1D): 4824
Dual Port Rams (RAM64X1D): 330
Simple Dual Port Rams (RAM64M): 7710
Dual Port Rams (RAM128X1D): 48
Block Rams : 833 of 1064 (78%)
DSP48s: 337 of 2016 (16%)
Global Clock Buffers: 15 of 32 (46%)
Mapping Summary:
Total LUTs: 141718 (46%)
Number of unique control sets: 272
Mapper successful!
Here's usage report from ISE (.mrp file):
Design Information
------------------
Command Line : map -ol high -t 4 -mt 2 -w -xe n -o ws6vpxcpe.ncd -pr b
-detail -power off -register_duplication off ws6vpxcpe.ngd
Target Device : xc6vsx475t
Target Package : ff1759
Target Speed : -1
Mapper Version : virtex6 -- $Revision: 1.55 $
Mapped Date : Tue Nov 22 06:37:46 2011
Interim Summary
---------------
Slice Logic Utilization:
Number of Slice Registers: 256,918 out of 595,200 43%
Number used as Flip Flops: 256,914
Number used as Latches: 4
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 116,504 out of 297,600 39%
Number used as logic: 76,438 out of 297,600 25%
Number using O6 output only: 37,253
Number using O5 output only: 1,728
Number using O5 and O6: 37,457
Number used as ROM: 0
Number used as Memory: 39,843 out of 122,240 32%
Number used as Dual Port RAM: 38,028
Number using O6 output only: 36,572
Number using O5 output only: 432
Number using O5 and O6: 1,024
Number used as Single Port RAM: 0
Number used as Shift Register: 1,815
Number using O6 output only: 1,623
Number using O5 output only: 0
Number using O5 and O6: 192
Number used exclusively as route-thrus: 223
Number with same-slice register load: 0
Number with same-slice carry load: 223
Number with other load: 0
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 271,978
Number with an unused Flip Flop: 40,952 out of 271,978 15%
Number with an unused LUT: 155,474 out of 271,978 57%
Number of fully used LUT-FF pairs: 75,552 out of 271,978 27%
Number of unique control sets: 6,630
Number of slice register sites lost
to control set restrictions: 25,471 out of 595,200 4%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
OVERMAPPING of BRAM resources should be ignored if the design is
over-mapped for a non-BRAM resource or if placement fails.
IO Utilization:
Number of bonded IOBs: 579 out of 840 68%
Number of LOCed IOBs: 473 out of 579 81%
IOB Flip Flops: 30
IOB Master Pads: 104
IOB Slave Pads: 104
Number of bonded IPADs: 2
Specific Feature Utilization:
Number of RAMB36E1/FIFO36E1s: 1,365 out of 1,064 128% (OVERMAPPED)
Number using RAMB36E1 only: 1,365
Number using FIFO36E1 only: 0
Number of RAMB18E1/FIFO18E1s: 231 out of 2,128 10%
Number using RAMB18E1 only: 231
Number using FIFO18E1 only: 0
Number of BUFG/BUFGCTRLs: 15 out of 32 46%
Number used as BUFGs: 12
Number used as BUFGCTRLs: 3
Number of ILOGICE1/ISERDESE1s: 202 out of 1,080 18%
Number used as ILOGICE1s: 10
Number used as ISERDESE1s: 192
Number of OLOGICE1/OSERDESE1s: 361 out of 1,080 33%
Number used as OLOGICE1s: 11
Number used as OSERDESE1s: 350
Number of BSCANs: 0 out of 4 0%
Number of BUFHCEs: 0 out of 216 0%
Number of BUFIODQSs: 24 out of 108 22%
Number of BUFRs: 0 out of 54 0%
Number of CAPTUREs: 0 out of 1 0%
Number of DSP48E1s: 175 out of 2,016 8%
Number of EFUSE_USRs: 0 out of 1 0%
Number of FRAME_ECCs: 0 out of 1 0%
Number of GTXE1s: 0 out of 36 0%
Number of IBUFDS_GTXE1s: 1 out of 18 5%
Number of LOCed IBUFDS_GTXE1s: 1 out of 1 100%
Number of ICAPs: 0 out of 2 0%
Number of IDELAYCTRLs: 27 out of 27 100%
Number of IODELAYE1s: 322 out of 1,080 29%
Number of LOCed IODELAYE1s: 48 out of 322 14%
Number of MMCM_ADVs: 4 out of 18 22%
Number of LOCed MMCM_ADVs: 3 out of 4 75%
Number of PCIE_2_0s: 0 out of 2 0%
Number of STARTUPs: 1 out of 1 100%
Number of SYSMONs: 0 out of 1 0%
Number of TEMAC_SINGLEs: 0 out of 4 0%
Mapping completed.
See MAP report file "design.mrp" for details.
Problem encountered during the packing phase.
Design Summary
--------------
Number of errors : 3
Number of warnings : 418
