Implementation

[chaiwat]

Running on ML506 evaluation board

Firstly, I design EDK system and implement the system by EDK, the implementation can be successful. After that, I create new ISE project and add "system.xmp" (EDK module) to be submodule in big system to add my own h/w design on top level, but error message is found during this implementation.

Before this time, I use same method to add EDK submodule in ISE project in ISE10 and ISE11 version, and it can implement successfully. So, this error is found when I upgrade to use ISE12 version.

Could anyone give me some suggestion about this problem? Is there any more special setting for ISE12 to implement EDK by using ISE flow?

The error message is shown as below.

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Processing BMM file "edkBmmFile.bmm" ...
ERROR:NgdBuild:989 - Failed to process BMM information edkBmmFile.bmm

Checking expanded design ...
ERROR:NgdBuild:604 - logical block 'system_i/RS232_Uart_1' with type
   'rs232_uart_1_wrapper' could not be resolved. A pin name misspelling can
   cause this, a missing edif or ngc file, case mismatch between the block name
   and the edif or ngc file name, or the misspelling of a type name. Symbol
   'rs232_uart_1_wrapper' is not supported in target 'virtex5'.
ERROR:NgdBuild:604 - logical block 'system_i/clock_generator_0' with type
   'clock_generator_0_wrapper' could not be resolved. A pin name misspelling can
   cause this, a missing edif or ngc file, case mismatch between the block name
   and the edif or ngc file name, or the misspelling of a type name. Symbol
   'clock_generator_0_wrapper' is not supported in target 'virtex5'.
ERROR:NgdBuild:604 - logical block 'system_i/xps_timer_1' with type
   'xps_timer_1_wrapper' could not be resolved. A pin name misspelling can cause
   this, a missing edif or ngc file, case mismatch between the block name and
   the edif or ngc file name, or the misspelling of a type name. Symbol
   'xps_timer_1_wrapper' is not supported in target 'virtex5'.
ERROR:NgdBuild:604 - logical block 'system_i/xps_intc_0' with type
   'xps_intc_0_wrapper' could not be resolved. A pin name misspelling can cause
   this, a missing edif or ngc file, case mismatch between the block name and
   the edif or ngc file name, or the misspelling of a type name. Symbol
   'xps_intc_0_wrapper' is not supported in target 'virtex5'.
ERROR:NgdBuild:604 - logical block 'system_i/DDR2_SDRAM' with type
   'ddr2_sdram_wrapper' could not be resolved. A pin name misspelling can cause
   this, a missing edif or ngc file, case mismatch between the block name and
   the edif or ngc file name, or the misspelling of a type name. Symbol
   'ddr2_sdram_wrapper' is not supported in target 'virtex5'.
ERROR:NgdBuild:604 - logical block 'system_i/util_ds_buf_0' with type
   'util_ds_buf_0_wrapper' could not be resolved. A pin name misspelling can
   cause this, a missing edif or ngc file, case mismatch between the block name
   and the edif or ngc file name, or the misspelling of a type name. Symbol
   'util_ds_buf_0_wrapper' is not supported in target 'virtex5'.
ERROR:NgdBuild:604 - logical block 'system_i/lmb_bram_if_cntlr_1' with type
   'lmb_bram_if_cntlr_1_wrapper' could not be resolved. A pin name misspelling
   can cause this, a missing edif or ngc file, case mismatch between the block
   name and the edif or ngc file name, or the misspelling of a type name. Symbol
   'lmb_bram_if_cntlr_1_wrapper' is not supported in target 'virtex5'.
ERROR:NgdBuild:604 - logical block 'system_i/npi_sata_0' with type
   'npi_sata_0_wrapper' could not be resolved. A pin name misspelling can cause
   this, a missing edif or ngc file, case mismatch between the block name and
   the edif or ngc file name, or the misspelling of a type name. Symbol
   'npi_sata_0_wrapper' is not supported in target 'virtex5'.
ERROR:NgdBuild:604 - logical block 'system_i/proc_sys_reset_0' with type
   'proc_sys_reset_0_wrapper' could not be resolved. A pin name misspelling can
   cause this, a missing edif or ngc file, case mismatch between the block name
   and the edif or ngc file name, or the misspelling of a type name. Symbol
   'proc_sys_reset_0_wrapper' is not supported in target 'virtex5'.
ERROR:NgdBuild:604 - logical block 'system_i/debug_module' with type
   'debug_module_wrapper' could not be resolved. A pin name misspelling can
   cause this, a missing edif or ngc file, case mismatch between the block name
   and the edif or ngc file name, or the misspelling of a type name. Symbol
   'debug_module_wrapper' is not supported in target 'virtex5'.
ERROR:NgdBuild:604 - logical block 'system_i/lmb_bram' with type
   'lmb_bram_wrapper' could not be resolved. A pin name misspelling can cause
   this, a missing edif or ngc file, case mismatch between the block name and
   the edif or ngc file name, or the misspelling of a type name. Symbol
   'lmb_bram_wrapper' is not supported in target 'virtex5'.
ERROR:NgdBuild:604 - logical block 'system_i/ilmb_cntlr' with type
   'ilmb_cntlr_wrapper' could not be resolved. A pin name misspelling can cause
   this, a missing edif or ngc file, case mismatch between the block name and
   the edif or ngc file name, or the misspelling of a type name. Symbol
   'ilmb_cntlr_wrapper' is not supported in target 'virtex5'.
ERROR:NgdBuild:604 - logical block 'system_i/dlmb_cntlr' with type
   'dlmb_cntlr_wrapper' could not be resolved. A pin name misspelling can cause
   this, a missing edif or ngc file, case mismatch between the block name and
   the edif or ngc file name, or the misspelling of a type name. Symbol
   'dlmb_cntlr_wrapper' is not supported in target 'virtex5'.
ERROR:NgdBuild:604 - logical block 'system_i/dlmb' with type 'dlmb_wrapper'
   could not be resolved. A pin name misspelling can cause this, a missing edif
   or ngc file, case mismatch between the block name and the edif or ngc file
   name, or the misspelling of a type name. Symbol 'dlmb_wrapper' is not
   supported in target 'virtex5'.
ERROR:NgdBuild:604 - logical block 'system_i/ilmb' with type 'ilmb_wrapper'
   could not be resolved. A pin name misspelling can cause this, a missing edif
   or ngc file, case mismatch between the block name and the edif or ngc file
   name, or the misspelling of a type name. Symbol 'ilmb_wrapper' is not
   supported in target 'virtex5'.
ERROR:NgdBuild:604 - logical block 'system_i/mb_plb' with type 'mb_plb_wrapper'
   could not be resolved. A pin name misspelling can cause this, a missing edif
   or ngc file, case mismatch between the block name and the edif or ngc file
   name, or the misspelling of a type name. Symbol 'mb_plb_wrapper' is not
   supported in target 'virtex5'.
ERROR:NgdBuild:604 - logical block 'system_i/microblaze_0' with type
   'microblaze_0_wrapper' could not be resolved. A pin name misspelling can
   cause this, a missing edif or ngc file, case mismatch between the block name
   and the edif or ngc file name, or the misspelling of a type name. Symbol
   'microblaze_0_wrapper' is not supported in target 'virtex5'.

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From error message, it seems that ISE cannot recognize that there is EDK system to be sub-module inside project and it cannot find system.ngc.

Thank you very much

[rohini.patil · Accepted solution]

Hello,

In synthesis process properties,

Check the read core option and point it to the path to implementation folder of EDK

Hope this will work for you

[chaiwat]

Thanks for your solution.

After I point option "Macro search path" to implementation folder, there is another error message to inform that there are multiple iobufs at MPMC pin within EDK. I thinks this error is caused from both EDK and ISE generate IOBUF to the same pin.

Now I can fins one solution for this problem, but it's rather complicate step to do, i.e.

1. Running normal operation to implement ISE including EDK until ISE12.3 showing error message like described as above.
2. Backup system.ngc from ise project folder.
3. Remove EDK module (system.xmp) from ise, clean up ISE, and copy system.ngc back to ise project folder.
4. Re-implement ISE project until successful.
5 Add EDK module (system.xmp) back to ISE project and re-implement until successful.

To run all above steps, it takes long time to make and debug. Is there any easier way to solve this problem.

[lsousa]

I also found this issue in 12.4.

Is there any easier way to solve the problem?

BR

L

[manvarjay]

Hey Guys I am having the same error when I do hardware co-simulation using system generator. I am using xilinx ISE13.2 and MATLAB 2010a.

I get this error when I use IP CORE of block RAM, otherwise without IP CORE it is working properly.

The error is as below

NgdBuild:604 - logical block 'sysgen_hwcosim_iface/sysgen_dut/blockram1_x0/black_box/core' with type  'br_core' could not be resolved. A pin name misspelling can cause this, a  missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'br_core' is not supported in target 'virtex5'.