03-01-2011 04:16 AM
WARNING:EDK - IPNAME: ppc405_virtex4, INSTANCE: ppc405_0 - PARAMETER: C_FASTEST_PLB_CLOCK has value DPLB1 specified in MHS, but tcl is overriding the value to DPLB0 - D:\users\xxx\projects\BCM\test\edk_13_test\edk\edk
03-02-2011 06:29 AM
Have you tried more than 1 design?
Does this happen on all designs?
Perhaps you could try an example design?
If this occurs consistently, then please try uninstall and re-install 13.1 if you have not already. If this occurs for this design only then please open a webcase at http://www.xilinx.com/support/clearexpress/websupp
03-02-2011 09:31 AM
Based on the warning messages that were being printed just before the failure, it appears to be a problem with constraint error handling. As a test, try rerunning with no constraints file.
03-03-2011 09:04 AM - edited 03-03-2011 09:05 AM
@ambrosef, basically I tried running 2 examples. But both included PowerPC and EDK subdesign.
@bwade. The constraint file was generated by BSB in EDK, it should be OK, I guess.
And I really can not afford to implement my design without constraints file...
I am targeting Virtex4FX.
03-04-2011 12:16 AM
Did I understand you correctly that you suggested to not include the ucf file in /data folder?
I did that (actually I deleted the content of that file) and that resulted in the following error log:
Process "Translate" completed successfully
Started : "Map".Running map...Command Line: map -intstyle ise -p xc4vfx60-ff1152-11 -global_opt off -cm area -ir off -pr off -c 100 -o edk_top_map.ncd edk_top.ngd edk_top.pcfUsing target part "4vfx60ff1152-11".ERROR:LIT:411 - IOBUFDS symbol "edk_i/DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v4_dd
As stated before, I am just trying to give 13.1 a test drive with BSB-generated hardware (ppc, ddr, ddr2, uart, gpio and ethernet).
03-11-2011 03:52 AM
I am running on exactly the same problem (ngdbuild crash) on a completely different machine.
Before: WinXP SP3 32-bit, 3GB RAM, ISE 13.1
Now: Win7 64-bit, 8GB RAM, ISE 13.1
The project that I tried to implement is basically a BSB-generated project for ML410,
without my modifications.
Do the tools produce a log file which could be useful to debug the problem?
Xilinx, would it be useful to you if I send you a complete project and you try to reproduce the problem?