Implementation

[dbaselt]

I'm trying to generate an IBIS file for a Spartan-6 so that I can do a signal integrity simulation for my PCB layout. So, to get to the point where I can use the IBISWriter tool, I created an empty project and then added DDR3 and MicroBlaze sources. Everything seemed to work but then Implement Design failed because of an IO standard mismatch. I haven't been able to manually set the IO standard with PlanAhead because the problem IOB is not listed as an I/O port.

This is what I've done:

1) In ISE Project Navigator, create a new Spartan-6 XC6SLX75 HDL project.
2) Add a New IP Source "MIG Virtex-6 and Spartan-6"
3) Add a new Embedded Processor source that includes a DDR3_SDRAM peripherial
4) Generate Top HDR Source
5) Synthesize-XST
6) Implement Design

Here's the error message that I get:

-------

ERROR:Place:864 - Incompatible IOB's are locked to the same bank 3
Conflicting IO Standards are:
IO Standard 1: Name = SSTL15_II, VREF = 0.75, VCCO = 1.50, TERM = NONE, DIR =
BIDIR, DRIVE_STR = NR
List of locked IOB's:
MCB_DDR3_zio
MCB_DDR3_dram_dq<0>
[...etc...]

IO Standard 2: Name = LVCMOS25, VREF = NR, VCCO = 2.50, TERM = NONE, DIR =
OUTPUT, DRIVE_STR = 12
List of locked IOB's:
mcbx_dram_ddr3_rst

These IO Standards are incompatible due to VCCO mismatch.

-------

I tried to use PlanAhead to manually set the IO standard, but it doesn't list mcbx_dram_ddr3_rst in the I/O Ports window. MCB_DDR3_dram_ddr3_rst is the closest match but the Xilinx tools seem to treat this as a different signal.

Am I doing something wrong? All the other signals seem to be correctly set up, it's just this one that's the problem.

[eschabor]

SSTL15_II (1.5V) and LVCMOS25 (2.5V) within a single bank is certainly not possible, that's easy to understand.

What I don't understand is why the signal mcbx_dram_ddr3_rst has been assigned the LVCMOS25 signalling standard - it should be SSTL15. ( I assume that signal is simply the DDR3 reset signal, which is the asynchronous reset input of DDR3 chips which uses SSTL15 signalling).

Which version of ISE are you using ?

Stephen Ecob
Silicon On Inspiration
Sydney Australia
www.sioi.com.au
$49 Spartan 6 board with 32MB DDR DRAM ?
http://www.sioi.com.au/shop/product_info.php/products_id/47

[dbaselt]

I'm using release 13.3.

I think the 2.5V I/O standard is just the default; that is, the memory interface generator didn't set the I/O standard for that one signal. All the other DDR3 signals were automatically set to 1.5V standards.

[eschabor]

Then I suggest adding an entry in your UCF to assign SSTL15 signalling to signal mcbx_dram_ddr3_rst - hopefully that will fix it.

[hirschdaumen]

It should be LVCMOS15, not SSTL15. The DDR3 reset pin is a CMOS input, not a SSTL input. Assigning SSTL15 to reset can lead to some nasty overshoot/undershoot in a SI simulation.

LVCMOS15 is what MIG assigns to reset.

[htsvn · Accepted solution]

Hi,

Refer this post.

http://forums.xilinx.com/t5/EDK-and-Platform-Studio/Problem-with-MCB-DDR3/td-p/195634

Thnx

[dbaselt]

To clarify, the solution was to add two lines to the file XYZ.mhs, where XYZ is the name of the microprocessor instance. To the first block of PORT declarations add:

PORT MCB_DDR3_dram_ddr3_rst = MCB_DDR3_dram_ddr3_rst, DIR = O

Delete the other line in this block that starts with PORT MCB_DDR3_dram_ddr3_rst .

To the last block of text (labeled BEGIN axi_s6_ddrx) add:

PORT mcbx_dram_ddr3_rst = MCB_DDR3_dram_ddr3_rst

It is then possible to implement the design.