05-14-2012 07:43 AM
I have updated to the latest version of the Xilinx lools on my Linux system.
If I compile my ISE (VHDL) project with 13.4 everything works fine. Comiling with 14.1 fails in step Maping with the following message:
ERROR:PhysDesignRules:1710 - Incomplete connectivity. The pin <PAD> of comp
block <logic/my_input_sync/pin_in_data<24>> is used and partially connected
to network <logic/my_input_sync/pin_in_data<24>>. All networks must have
complete connectivity to the comp hierarchy and the connectivity for this pin
must be removed or completed.
Repeated for each bit of the vector.
The signal is comming form the UCF (Pin) and routed to a FD component coded as following:
GENERIC( INIT : bit := '0' );
PORT ( Q : OUT std_logic;
C : IN std_logic;
D : IN std_logic);
attribute iob of FD: component is "true";
attribute box_type of FD : component is "black_box";
make_data_iob_A : for n in 27 downto 0 generate -- make the iobs for the data pins
in_ff : FD
generic map ( INIT => '1' )
port map ( D => p_data_A(n),
Q => s_diob_A(n),
C => clk_A );
end generate make_data_iob_A;
Has something changed with the FD component, or what could be the problem?
How can I make it compile with the new version?
Thank you for your answer.
05-15-2012 12:55 PM
I suggest that you file a webcase to have this investigated. Based on the CRs for similar issues in the past, it's very likely that Map will run OK with the -ignore_keep_hierarchy option.