Implementation

[drat]

Good morning

I'm trying to constraint the pins of LUTs in proxy logic but it is not working, may you anybody advise me how to use LOCK_PINS constraint (in UCF file) correctly. It is syntax example from Xilinx Constraint guide:  INST I_894 LOCK_PINS=I3:A1,I2:A4; What do mean "I3" and "A1" etc..

Thank you very much for yours answer

               Drat

[ywu]

Trying setting LOCK_PINS=ALL

I0, I1, I2, I3 are the pin names on a LUT primitive in the device library (check the libraries guide for your specific target device)

A1, A3, A3, A4 are the pin names used for the device model of LUT in FPGA. You will see those pin names when you look at a LUT inside FPGA_EDITOR.

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drat wrote:

Good morning

I'm trying to constraint the pins of LUTs in proxy logic but it is not working, may you anybody advise me how to use LOCK_PINS constraint (in UCF file) correctly. It is syntax example from Xilinx Constraint guide:  INST I_894 LOCK_PINS=I3:A1,I2:A4; What do mean "I3" and "A1" etc..

Thank you very much for yours answer

               Drat

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