Hi,
A design I'm working with won't go through MAP. I'm running ISE 13.1. I get the following errors:
Mapping design into LUTs...
ERROR:TSDatabase:19 - Processing TIMESPEC definition
TS_D2_TO_T2=FROM:D2_CLK:TO:FFS:TIG:
No TNM, TPSYNC or user group named "D2_CLK" is defined.
ERROR:TSDatabase:19 - Processing TIMESPEC definition
TS_J2_TO_D2=FROM:FFS:TO:D2_CLK:TIG:
No TNM, TPSYNC or user group named "D2_CLK" is defined.
ERROR:TSDatabase:19 - Processing TIMESPEC definition
TS_J3_TO_D2=FROM:FFS:TO:D2_CLK:TIG:
No TNM, TPSYNC or user group named "D2_CLK" is defined.
ERROR:TSDatabase:19 - Processing TIMESPEC definition
TS_J4_TO_D2=FROM:FFS:TO:D2_CLK:TIG:
No TNM, TPSYNC or user group named "D2_CLK" is defined.
INTERNAL_ERROR:Pack:pkibangm.c:2584:1.87 - 4 timespec errors found
It's a large design on a Virtex 6. There's a PCIe endpoint (with large portions of code directly from Xilinx) and a number of Coregen units.
Now, I don't know what to do with these errors. In the ucf file, there are no TIMESPEC definitions like the ones complained about ("TS_D2_TO_T2" and so on) or anything similar. There's just one ucf file in the project. There's also no TNM or similar named to "D2_CLK". So I just don't understand what the TIMESPEC comes from in the first place?
I searched for the pattern "*TS_J2*" in all files of the project. I listed the output below this message. It's found in four files: Three reporting the error (xmsg, the .map and .mpr files), *and* once in the Synthesis Report. The latter lists a timing constraint, "TS_J2_TO_D2 = FROM TIMEGRP "FFS" TO TIMEGRP "D2_CLK" TIG;", but where does the synthesis tool get this from since I can't find anywhere where this definition is inputted to the tools? Also, synthesis don't complain about missing "D2_CLK" so I guesse it is found somewhere. But I can't understand that either, since if I search for the pattern "D2_CLK" (command "grep -i -r -C 3 D2_CLK .") it finds exactly the same entries as searching for TS_J2 - so I can't understand what D2_CLK is or where it comes from either.
Any help is appreciated!
Carl
<in project directory:>
$ grep -i -r -C 3 TS_J2 .
./_xmsgs/map.xmsgs-</arg>No TNM, TPSYNC or user group named "<arg fmt="%s" index="2">D2_CLK</arg>" is defined.
./_xmsgs/map.xmsgs-</msg>
./_xmsgs/map.xmsgs-
./_xmsgs/map.xmsgs:<msg type="error" file="TSDatabase" num="19" delta="new" ><arg fmt="%z" index="1">Processing TIMESPEC definition TS_J2_TO_D2=FROM:FFS:TO:D2_CLK:TIG:
./_xmsgs/map.xmsgs-</arg>No TNM, TPSYNC or user group named "<arg fmt="%s" index="2">D2_CLK</arg>" is defined.
./_xmsgs/map.xmsgs-</msg>
./_xmsgs/map.xmsgs-
--
./xilinx_pcie_2_0_ep_v6.syr- (51.1% logic, 48.9% route)
./xilinx_pcie_2_0_ep_v6.syr-
./xilinx_pcie_2_0_ep_v6.syr-=========================================================================
./xilinx_pcie_2_0_ep_v6.syr:Timing constraint: TS_J2_TO_D2 = FROM TIMEGRP "FFS" TO TIMEGRP "D2_CLK" TIG;
./xilinx_pcie_2_0_ep_v6.syr- Clock period: 1.086ns (frequency: 920.641MHz)
./xilinx_pcie_2_0_ep_v6.syr- Total number of paths / destination ports: 15 / 15
./xilinx_pcie_2_0_ep_v6.syr- Number of failed paths / ports: 0 (0.00%) / 0 (0.00%)
--
./xilinx_pcie_2_0_ep_v6_map.map- TS_D2_TO_T2=FROM:D2_CLK:TO:FFS:TIG:
./xilinx_pcie_2_0_ep_v6_map.map- No TNM, TPSYNC or user group named "D2_CLK" is defined.
./xilinx_pcie_2_0_ep_v6_map.map-ERROR:TSDatabase:19 - Processing TIMESPEC definition
./xilinx_pcie_2_0_ep_v6_map.map: TS_J2_TO_D2=FROM:FFS:TO:D2_CLK:TIG:
./xilinx_pcie_2_0_ep_v6_map.map- No TNM, TPSYNC or user group named "D2_CLK" is defined.
./xilinx_pcie_2_0_ep_v6_map.map-ERROR:TSDatabase:19 - Processing TIMESPEC definition
./xilinx_pcie_2_0_ep_v6_map.map- TS_J3_TO_D2=FROM:FFS:TO:D2_CLK:TIG:
--
./xilinx_pcie_2_0_ep_v6_map.mrp- TS_D2_TO_T2=FROM:D2_CLK:TO:FFS:TIG:
./xilinx_pcie_2_0_ep_v6_map.mrp- No TNM, TPSYNC or user group named "D2_CLK" is defined.
./xilinx_pcie_2_0_ep_v6_map.mrp-ERROR:TSDatabase:19 - Processing TIMESPEC definition
./xilinx_pcie_2_0_ep_v6_map.mrp: TS_J2_TO_D2=FROM:FFS:TO:D2_CLK:TIG:
./xilinx_pcie_2_0_ep_v6_map.mrp- No TNM, TPSYNC or user group named "D2_CLK" is defined.
./xilinx_pcie_2_0_ep_v6_map.mrp-ERROR:TSDatabase:19 - Processing TIMESPEC definition
./xilinx_pcie_2_0_ep_v6_map.mrp- TS_J3_TO_D2=FROM:FFS:TO:D2_CLK:TIG:
$
