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Visitor
icyrock
Posts: 4
Registered: ‎11-07-2009
0

Map phases description

When I do MAP on ISE 11, the process goes up to "Phase 9.8.  Global Placement"  and then runs for hours in this phase.

I can not decide, what to optimize in my design, because I can not figure out, what problem MAP engine tries to solve in such a long time. Hence, my question: "do Xilinx have any open documentation about phases of MAP process in detail?"

 

I have failed to find one.

 

 

Expert Contributor
evgenis1
Posts: 338
Registered: ‎12-03-2007
0

Re: Map phases description

Hi,

 

As far as I know, there isn't detailed documentation on the MAP phases.

 

But it's not unusual that MAP is running for hours, as soon as it completes.

Can you provide some more information about your design: what FPGA, max clock frequency, how utilized the design is, is it floorplanned. 

 

 

Thanks,

Evgeni

Xilinx Employee
sarithas
Posts: 73
Registered: ‎08-23-2008
0

Re: Map phases description

Do you have any global resources placement constraints (like clock pins, BUFG)? if so can you please try running the design by removing these constraints. 

 

this helps to narrow down the issue. 

 

Can you also try with the bigger device, there may be some problem with fitting the design in the device?

 

please try with this two options.

 

Thanks

Xilinx Employee
siktapany
Posts: 120
Registered: ‎06-11-2009
0

Re: Map phases description

Global placement phase tries to do a global placement of your deisgn mostly after the local placement. It usually takes time if the deisgn is huge or if you use a larger device.

 

You could also try in the latest version of tools( 12.4).  Trying without the ucf could give an hint if its the constraints inhibiting the placement or deisgn issue.

Visitor
icyrock
Posts: 4
Registered: ‎11-07-2009
0

Re: Map phases description

My device is Virtex 4 sx55.

 

My design is heavily utilized: 76% LUT, 62% FF, 97 % RAMB, DSP48 75%. 250 000 nets. And that is why I need a hint about optimization priorities for me. Timing is only 80 MHz.

 

I made floorplannig only for RAMBs, DSPs and ports to direct implementation, not constraining it too strictly.

 

P.S.

After a night calculating, MAP reported me it was unable to place FFs. Its seems strange, since there is enough room for FFs left and they were not constrained at all.

Expert Contributor
awillen
Posts: 687
Registered: ‎11-29-2007

Re: Map phases description

 


P.S.

After a night calculating, MAP reported me it was unable to place FFs. Its seems strange, since there is enough room for FFs left and they were not constrained at all.


 

That might be because there are too many unique control sets. Remember that only one unique control set is allowed per slice, so FFs might go unused.

 

 

Adrian



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Xilinx Employee
siktapany
Posts: 120
Registered: ‎06-11-2009
0

Re: Map phases description

http://www.xilinx.com/support/answers/35539.htm

Check out this answer on Place:543 error giving insight on why tool might have problems placing FFs.