Implementation

[stu_abrams]

I could meet timing just fine with the LX45T -2 part but with the exact same design and constraints, the LX100T -3 part will not meet timing.  I have opened up FPGA editor and noticed that it is choosing FFs so far from the ODDR that it can't make it in time, incurring a 3+ ns net delay when my clock is running at 368 MHz...Any suggestions?  I have added registers in hope that the tool would find the optimal location but it just won't.

Any suggestions?

thanks,
Stu 

[bassman59]

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stu_abrams wrote:

I could meet timing just fine with the LX45T -2 part but with the exact same design and constraints, the LX100T -3 part will not meet timing.  I have opened up FPGA editor and noticed that it is choosing FFs so far from the ODDR that it can't make it in time, incurring a 3+ ns net delay when my clock is running at 368 MHz...Any suggestions?  I have added registers in hope that the tool would find the optimal location but it just won't.

Any suggestions?

thanks,
Stu 

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Unfortunately, you might have to do some floorplanning.

[stu_abrams]

I have tried floorplanning, LOC'ing the registers to specific slices, but the tool won't ever get to timing closure.  What's odd is that the Clock Regions X0Y0 and X1Y0 are both used for my ODDR Clocking but it won't place any of my flops in those regions...unless I specifically LOC those registers.

[bwade]

If the design has very low utilization in the new part, try this solution:

http://www.xilinx.com/support/answers/33021.htm