Implementation

[net.worker]

Hello community,

this is no April's Fools joke - I have some issues achieving timing closure, depending on which time of the day I start the implementation.

Of course, there's no black magic at work, it's rather that the build date of the design is updated automatically. This build date is readable as a 32 bit vector over an external serial bus. There are a lot of other registers in this register set, and of course the address decoding multiplexer is growing quite large.

Now, as the build date is a constant, no registers are allocated, but I presume the output function for the build date address is contained in the mux logic (i.e. returning a constant value for the build date address). This function of course changes with the time of day, impacting the P&R outcome.

Since I wanted to decouple this build date logic so that I can get the same result any time of day, my idea was to force the constant values into registers, which would then be normally selected by the address as any other register in there.

This is the component I wrote which I hoped would infer the forced registers:

library ieee;
use ieee.std_logic_1164.all;

library UNISIM;
use UNISIM.VComponents.all;

entity const_reg_32 is

   generic (
      width : positive                      := 32;
      value : std_logic_vector(31 downto 0) := x"00000000");

   port (
      clk : in  std_logic;
      q   : out std_logic_vector(31 downto 0));

end entity const_reg_32;

architecture str of const_reg_32 is

   function sl2bit (
      d : std_logic)
      return bit is
   begin  -- function sl2bit
      if d = '1' then
         return '1';
      else
         return '0';
      end if;
   end function sl2bit;
   
   attribute KEEP : STRING ;
   attribute KEEP of Q : SIGNAL is "TRUE"; -- attribute on signal
   attribute KEEP of gen : LABEL is "TRUE"; -- attribute on component   
   
begin  -- architecture str
   
   gen : for i in width-1 downto 0 generate
      attribute KEEP of regbit : LABEL is "TRUE"; -- attribute on instance
   begin 
      regbit : FD
         generic map (
            INIT => sl2bit(value(i)))
         port map (
            Q => Q(i),                  -- Data output
            C => clk,                   -- Clock input
            D => value(i)               -- Data input
            );
   end generate gen;
   
end architecture str;

 When looking in the technology viewer, the FD type registers (identified by 'regbit') are all visible.
However, when searching for the net names in FPGA Editor or Timing Analyzer, none are to be found (tried some variants as well, FF instance, Q net name...). Also, the bus output in the instantiating VHDL module has a KEEP attribute.

ISE actually tells me it's going to throw the registers away:

WARNING:Xst:1293 - FF/Latch <myhierarchy/const_reg_32_2/gen[0].regbit> has a constant value of 1 in block <myblock>. This FF/Latch will be trimmed during the optimization process.

Are the registers gone, or is it just that I can't find them anymore using these tools?

Will this idea of using registers as constants work at all, or do you not reccomend doing this? If not, what's preferrable?

Many thanks,

Florian

[mcgett]

The registers in your code are initialized to a constant with the same constant as the data, so it resolves to a constant  and the register removed to save space.  This will then allow for additional optimizations on the rest of your design with either more or less logic optimized out impact your timing.

BTW that is a lot of code for something that is very simple, it could have been written like this:

library ieee;
use ieee.std_logic_1164.all;

library UNISIM;
use UNISIM.VComponents.all;

entity const_reg_32 is

   generic (
       value : std_logic_vector(31 downto 0) := x"00000000");
   port (
      clk : in  std_logic;
      q   : out std_logic_vector(31 downto 0) := value);

end entity const_reg_32;

architecture str of const_reg_32 is
   
begin  -- architecture str

   process (clk)
   begin
      q = value;
   end process
      
end architecture str;

 or really just like this:

library ieee;
use ieee.std_logic_1164.all;

library UNISIM;
use UNISIM.VComponents.all;

entity const_reg_32 is

   generic (
       value : std_logic_vector(31 downto 0) := x"00000000");
   port (
      q   : out std_logic_vector(31 downto 0) := value);

end entity const_reg_32;

architecture str of const_reg_32 is
   
begin  -- architecture str

  q <= value;
      
end architecture str;

[bwade · Accepted solution]

You should be able to block the optimization of the FF using the UCF constraint:

INST "myhierarchy/const_reg_32_2/gen[0].regbit" S;

[net.worker]

Thanks bwade, that did the trick!

I was able to attach this constraint in VHDL like this (if I read cgd.pdf correclty, that's the SAVE NET FLAG constraint):

attribute S    of regbit : LABEL is "TRUE"; -- attribute on instance

 The FFs were retained.

Now I can continue and see if this approach helps in making P&R indepedent of the time of day.