Implementation

[wg]

Hello all,

I am designing a system with S3ADSP. I have some Area_Group constraints for two modules. The PAR gives me this error:

"
ERROR:Place:293 - The following 11 components are required to be placed in a specific relative placement form. The
   required relative coordinates in the RPM grid (that can be seen in the FPGA Editor) are shown in brackets next to the
   component names. Due to placement constraints it is impossible to place the components in the required form.
"

I get similar error 3 more times for different components. Please tell me how I should go about resolving this issue and which tools I should use?


Regards,

wg

[bwade]

This error occurs when the placer is unable to assemble a multi-component structure to satisfy the connectivity restrictions of the components involved. Examples would be carry chains, shift chains, cascaded DSPs, etc. One possibility is that your area group constraints are preventing the structure from being placed appropriately. The error message tells you which components are involved. From that you should be able to determine the type of structure involved and then figure out what is causing the interference.

[wg]

Hello bwade,

Thanks for your reply. I have placement constraints for MPMC module(SDRAM_CUSTOM) and another module. I am getting the following error:

ERROR:Place:293 - The following 11 components are required to be placed in a specific relative placement form. The
   required relative coordinates in the RPM grid (that can be seen in the FPGA Editor) are shown in brackets next to the
   component names. Due to placement constraints it is impossible to place the components in the required form.
        SLICEL Inst_system/mb_plb_Sl_rdDBus<321> (0, 0) - Net
        SLICEL Inst_system/npi_pcore_0_MY_NPI_RdFIFO_Data<29> (0, 1)  constrained by statement COMPGRP
   "AG_Inst_system/SDRAM_CUSTOM.SLICE" LOCATE = SITE
           "SLICE_X27Y173:SLICE_X92Y81" LEVEL 4; - Net
        SLICEL Inst_system/matrix_multiplier_1/matrix_multiplier_1/USER_LOGIC_I/Madd_adder_out_mem_2_add0000_Madd_cy<5>
   (0, 2) - Part of Carry Chain
        SLICEL Inst_system/matrix_multiplier_1/matrix_multiplier_1/USER_LOGIC_I/Madd_adder_out_mem_2_add0000_Madd_cy<7>
   (0, 3) - Part of Carry Chain
        SLICEL Inst_system/matrix_multiplier_1/matrix_multiplier_1/USER_LOGIC_I/adder_out_mem_2_8 (0, 4) - DFF
        SLICEL Inst_system/matrix_multiplier_1/matrix_multiplier_1/USER_LOGIC_I/adder_out_mem_2_10 (0, 5) - DFF
        SLICEL Inst_system/matrix_multiplier_1/matrix_multiplier_1/USER_LOGIC_I/adder_out_mem_2_12 (0, 6) - DFF
        SLICEL Inst_system/matrix_multiplier_1/matrix_multiplier_1/USER_LOGIC_I/adder_out_mem_2_14 (0, 7) - DFF
        SLICEL Inst_system/matrix_multiplier_1/matrix_multiplier_1/USER_LOGIC_I/adder_out_mem_2_16 (0, 8) - DFF
        SLICEL Inst_system/matrix_multiplier_1/matrix_multiplier_1/USER_LOGIC_I/adder_out_mem_2_18 (0, 9) - DFF
        SLICEL Inst_system/matrix_multiplier_1/matrix_multiplier_1/USER_LOGIC_I/adder_out_mem_2_20 (0, 10) - DFF

I am getting 3 more similar errors all related to the MPMC placement constraint. Following are the observations:
1. The components listed are nets, carry chain and DFF.
2. The error message mentions FPGA Editor. When the mapping is done, I double-click 'Manually Place and Route(FPGA Editor)' from the ISE process, the FPGA editor opens the .ncd file, but then it doesn't display anything in the edit window. So I am not able to see the RPM grid. Can I see the RPM grid in FloorPlanner?


Regards,

wg

[bwade]

You're not seeing anything in FPGA Editor because the design is not placed. Don't worry about examining the grid system as the rules for carry chain placement are simple, the slices need to be placed in vertically adjacent sites. The carry chain is only 11 slices tall and should easily fit within your area group range. The only explanation I can think of is that the FFs involved are clocked by a BUFG  that is locked to a side BUFG site that can't reach the clock regions you have constrained the area group to. Check out the clock involved as that appears to be the only possible conflict.