05-07-2012 03:02 AM
I'm trying to implement a full-duplex single lane Aurora module (v6.2) using ISE 13.4
I want to connect two spartan6 xc6slx150t and I'm trying with a 600Mb lane rate
to simulate the communication, I instantiated two aurora module and connected each other
in simulation line_up goes high, but channel_up remains low
I checked the following signals in lane_init_sm_i:
and they seems to work fine, ready_r goes high and then line_up is asserted
I checked the following in channel_init_sm:
reset_channel -> goes down after line_up is up
wait_for_lane_up_r -> goes down
verify_r -> goes up
all_lanes_v_r -> remains low
got_first_v_r -> remains low
bad_v_r -> remains low
ready_r -> remains low
I'm using the clock_module and the standard_cc_module generated with the aurora core.
all the clock signals are toggling correctly
the simulation tool is ISIM
do you have any ideas on how to fix the problem?
10-15-2012 10:27 PM
im facing same problem what u have faced earlier..... No lane up and Channel Up going high.....
Im using virtex7 FPGA and ISE 14.1....
plz help me to come out of this issues....