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Problem with clock generator (wizard)
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06-05-2012 04:02 PM
Hi,
I'm facing an error, which I can't solve at all.
I'm using XPS 12.3 with MicroBlaze Processor and one user core (ff_0), which I want to run with a different frequency than the system. I tried the clock wizard and everything worked well until now:
Suddenly I am getting the following error message:
"Please make sure the core specific logic for the following components is in sync with the system clocking: proc_sys_reset_0, ff_0"
ff_0 is my IP and I'm using a specific clock for it, which I wanted to change.
The other clocks are called: microblaze_0 for the processor,
slowest_sync_clk for proc_sys_reset_0,
and my_clk for ff_0.
This error occurs even with 100MHz for MicroBlaze, proc_sys_reset_0 and ff_0.
If ff_0 is deleted, this error still occurs, with proc_sys_reset_0.
Can anyone give me a hint, what went wrong? Why aren't these components in sync with the system clocking? Where do I have to search for the solution?
Thank you very much in advance!
LG, achttausendmark
Re: Problem with clock generator (wizard)
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06-05-2012 04:51 PM
When I try to generate the Bitstream, I get the following error in the console:
ERROR:ConstraintSystem:59 - Constraint <Net fpga_0_clk_1_sys_clk_pin TNM_NET =
sys_clk_pin;> [system.ucf(5)]: NET "fpga_0_clk_1_sys_clk_pin" not found.
Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <Net fpga_0_clk_1_sys_clk_pin LOC = AH15
|> [system.ucf(7)]: NET "fpga_0_clk_1_sys_clk_pin" not found. Please verify
that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD=LVCMOS33;> [system.ucf(7)]:
NET "fpga_0_clk_1_sys_clk_pin" not found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
ERROR:Xflow - Program ngdbuild returned error code 2. Aborting flow execution...
I never got that error before...
Can anyone help?
Re: Problem with clock generator (wizard)
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06-05-2012 05:16 PM
This kind of error occurs because the specified net doesn't match the name in synthesized netlist.
Please make sure the input clock of clock wizard "fpga_0_clk_1_sys_clk_pin" is made external.











