Implementation

[rediboy]

Hi,

I'm facing a failure when the compiler trying to route "gtxs_module_0_Q4_CLK1_MGTREFCLK_PAD_N_IN_pin_IBUF".(Passing Synthesize, Translate and Map, but failing PAR without error message and with warning message fail to route "gtxs_module_0_Q4_CLK1_MGTREFCLK_PAD_N_IN_pin_IBUF".)

In my work, Virtex 6 (FF1156) is being used where 4 GTXs (in QUAD115) are configured as transmitter and REFCLK1 Q4 is selected for all the GTXs.

The GTXs are initiated in use_logic.vhd file and its input clock (REFCLK1 Q4 ) is routed in from system_top as external signals.

And Pin assignment is as follows (in ucf file)

May I know What I should do to resolve this problem?

Thanks

  ################################## Clock Constraints ##########################

NET "q4_clk1_refclk_i" TNM_NET = "q4_clk1_refclk_i";

TIMESPEC "TS_q4_clk1_refclk_i" = PERIOD "q4_clk1_refclk_i" 6.4;

# User Clock Constraints

NET "gtx0_txusrclk_i" TNM_NET = "gtx0_txusrclk_i";
TIMESPEC "TS_gtx0_txusrclk_i" = PERIOD "gtx0_txusrclk_i" 7.407;

NET "gtx0_txusrclk2_i" TNM_NET = "gtx0_txusrclk2_i";
TIMESPEC "TS_gtx0_txusrclk2_i" = PERIOD "gtx0_txusrclk2_i" 3.704;

#################### locs for top level ports (ML623 Board) ###################

####################### GTX reference clock constraints #######################

NET gtxs_module_0_Q4_CLK1_MGTREFCLK_PAD_N_IN_pin  LOC=F5;

NET gtxs_module_0_Q4_CLK1_MGTREFCLK_PAD_P_IN_pin  LOC=F6;

################################# mgt wrapper constraints #####################

##---------- Set placement for gtx0_gtx_wrapper_i/GTX_DUAL ------

INST "gtxs_module_0/gtxs_module_0/USER_LOGIC_I/GTX_i/gtx0_GTX_i/gtxe1_i" LOC=GTXE1_X0Y12;

##---------- Set placement for gtx1_gtx_wrapper_i/GTX_DUAL ------

INST "gtxs_module_0/gtxs_module_0/USER_LOGIC_I/GTX_i/gtx1_GTX_i/gtxe1_i" LOC=GTXE1_X0Y13;

##---------- Set placement for gtx2_gtx_wrapper_i/GTX_DUAL ------

INST "gtxs_module_0/gtxs_module_0/USER_LOGIC_I/GTX_i/gtx2_GTX_i/gtxe1_i" LOC=GTXE1_X0Y14;

##---------- Set placement for gtx3_gtx_wrapper_i/GTX_DUAL ------

INST "gtxs_module_0/gtxs_module_0/USER_LOGIC_I/GTX_i/gtx3_GTX_i/gtxe1_i" LOC=GTXE1_X0Y15

[mcgett]

> I'm facing a failure when the compiler trying to route "gtxs_module_0_Q4_CLK1_MGTREFCLK_PAD_N_IN_pin_IBUF".

> (Passing Synthesize, Translate and Map, but failing PAR without error message and with warning message fail to

>  route "gtxs_module_0_Q4_CLK1_MGTREFCLK_PAD_N_IN_pin_IBUF".)

It appears that something went wrong in synthesis and an IBUF was added before the IBUFDS_GTXE1 that should be used for the MGT (GTX) REFCLK.

Note: In the future please include the exact ERROR message that is report from tools along with the ISE version.