10-16-2011 05:14 PM - edited 10-16-2011 05:19 PM
I'm running smartxplorer on a design to get an implementation that meets timing constraints on a Virtex 6 FPGA and I see something very odd. For one of the strategies, I get a " - 0.440 " WorstCaseSlack but the timing score is zero. Smartxplorer picks this strategy as the best strategy since the timing score is zero. When I check the Post PAR Timing Report, there is no constraint violation, but the design summary [the table with all the synthesis info] shows that i have one failing constraint. I have attached a picture showing the result of smartxplorer.
Can someone explain why this is happening?
10-16-2011 08:12 PM
SmartXplorer uses the timing report for the final resorts so it's odd that it would report no timing score if the timing report says otherwise. Check your .par and .twr files to compare the timing numbers. PAR/TRCE timing score mismatches can happen either due to a timing bug or because the -to switch was used to pass options that change the score. If you are encountering the bug I suggest you open a webcase to have the issue investigated.
05-01-2012 09:40 PM
I see the same behavior for a design on the ML-605 board-- Timing Score 0, but an obvious timing error as indicated by WorseCaseSlace (the period constraint in 4.096 ns). I'll submit a Web Case.
05-02-2012 09:13 AM
Compare the .par and .twr files in the results directory. Does the .par file show a zero timing score and the .twr a non-zero score? Was a trce option used that accounts for that difference? If so, that is a user issue. If not, a webcase should be opened to investigate the timing discrepency between par and trce.
08-31-2012 01:53 AM
cross check the speed grade chosen in ur 'Translate' option and -to " -s x" option in ur 'Smartxlplorer' switch. This speed grade mismatch could lead to negative timing slack and zero timing score in ur Smartxlorer result. (Because of this mismatch another possible situation is positive slack and non-zero timing score).