Implementation

[zecary]

I'm designing a network on chip in which a fifo controller is in charge of one FWFT fifo to decide when to read from or write to fifo.

in the VHDL code of this fifo controller, there are two assignment statements:

    eop_wr  <= pkt_wr_EOP when pkt_we = '1' else '0';
    eop_rd  <= pkt_rd_EOP when pkt_re = '1' else '0';

pkt_wr, pkt_rd_EOP, pkt_we and pkt_re are the inputs of fifo controller.

When I implement my code I get some warnings telling me some singals don't have drivers. I checked the KEEP HIERARCHY, and opened the Technology Schematic to check the mistake signals, then I found that the the missing driver problem is because my "eop_wr" doesn't have a drive BUT "eop_rd" has.

In this image, I highlight the "eop_rd" output

In this image, I tried to highlight the input and output of statement for "eop_wr". Hope this one clear enough. There should be a LUT like "eop_rd" have. But there isn't.

What makes me confused is that why two same "when else" statements could result in differerent implementations. Where is my problem

[hgleamon1]

Exactly what messages do you get? You should copy and paste them here.

What does the XST report state after synthesis?

It looks to me like that the eop_wr signal has been optimised away but the input/output ports maintain because they exist at an entity level.

Without being able to see exactly how all of your logic interacts (e.g. where do pkt_wr_EOP and pkt_we come from? How do those signals change?), it is difficult to state why the implementation is different.

What can you see when you simulate pre/post_synthesis?

Regards,

Howard

[zecary]

Howard

Thanks for you response. I find the problem. It's due to that this signal doesn't drive any signals in the very upper level component. But why the compiler didn't give me a warning like the signal doesn't have a load.

I still have a small problem that when I try to implememt one of my component, I get two warnings like:

WARNING:NgdBuild:452 - logical net 'p01_vc/vc_req_id<1><0>' has no driver
WARNING:NgdBuild:452 - logical net 'p01_vc/vc_req_id<0><1>' has no driver

There two signals actully are created as virtual channel id that used in sub-component. They don't connect to any drivers.

    gen_vcids : process(rst,clk)
    begin
        lgen : for I in NOCEM_NUM_VC-1 downto 0 loop
              vc_myid_conv(I) <= CONV_STD_LOGIC_VECTOR(2**I, NOCEM_VC_ID_WIDTH);
        end loop;
    end process;

Will these warning affect my final PAR design? Or they'll be translate to functional LUT.

[hgleamon1]

Firstly, I cannot tell how vc_req_id and vc_myid_conv are related. It is impossible for me to say why the tools have issued a warning other than to say that the tools are not often wrong in these matters.

Ngdbuild:452 is a warning to alert the designer to a possibly unconnected signal. If this is important, then you should take steps to avoid it. A driverless signal will likely not be routed by PAR. A driverless signal is one that has no input to its value. You should consider how your loop is DRIVING the value of that signal.

Regards,

Howard