Implementation

[elahrairah]

I am using netgen to create post-PAR simulation models. I was wondering if there is any way to get netgen (or some other tool) to ouput the information about which signals go through which switch boxes. I can see this visually with FPGA Editor but wondered if there was a text-based form of that information.

[austin · Accepted solution]

e,

Look at the .xdl format, or the .ngc format, or convert the design to .edif format.

[elahrairah]

Thanks! I used the xdl command xdl -ncd2xdl to get the XDL format, exactly what I needed.

-Megan