Hi,
in ISE 11.4, when I instantiate a hard macro I get the following map crash during implementation:
Release 11.4 Map L.68 (nt)
Xilinx Mapping Report File for Design 'top'
Design Information
------------------
Command Line : map -ise testcortexsynth.ise -intstyle ise -p
xc5vlx50t-ff1136-1 -w -logic_opt off -ol high -t 1 -register_duplication off
-global_opt off -mt off -cm area -ir off -pr off -lc off -power off -o
top_map.ncd top.ngd top.pcf
Target Device : xc5vlx50t
Target Package : ff1136
Target Speed : -1
Mapper Version : virtex5 -- $Revision: 1.51.18.1 $
Mapped Date : Tue Apr 27 15:26:18 2010
EXCEPTION:Pds:Pds_PdmVccGndMgr.c:526:1.7 - Corrupt Database.
Design Summary
--------------
Number of errors : 1
Number of warnings : 0
Section 1 - Errors
------------------
EXCEPTION:Pds:Pds_PdmVccGndMgr.c:526:1.7 - Corrupt Database.
FATAL_ERROR:Map:Portability/export/Port_Main.h:159:1.27 - This application has
discovered an exceptional condition from which it cannot recover. Process
will terminate. For technical support on this issue, please open a WebCase
with this project attached at http://www.xilinx.com/support.
Section 2 - Warnings
--------------------
EXCEPTION:Pds:Pds_PdmVccGndMgr.c:526:1.7 - Corrupt Database.
Section 3 - Informational
-------------------------
INFO:MapLib:564 - The following environment variables are currently set:
INFO:MapLib:591 - XIL_MAP_NOCLIP_ON_ALL_SIGS_U Value: 1
INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
can be dramatically reduced by designating them as fast outputs.
INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
0.000 to 85.000 Celsius)
INFO:Pack:1720 - Initializing voltage to 0.950 Volts. (default - Range: 0.950 to
1.050 Volts)
EXCEPTION:Pds:Pds_PdmVccGndMgr.c:526:1.7 - Corrupt Database.
Section 4 - Removed Logic Summary
---------------------------------
1 block(s) optimized away
Section 5 - Removed Logic
-------------------------
Optimized Block(s):
TYPE BLOCK
VCC XST_VCC
EXCEPTION:Pds:Pds_PdmVccGndMgr.c:526:1.7 - Corrupt Database.
The Top vhdl module I have in the project reads like this:
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:16:58 04/27/2010
-- Design Name:
-- Module Name: top - beh
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity top is
Port ( Inputs : in STD_LOGIC_VECTOR (0 to 119);
Outputs : out STD_LOGIC_VECTOR (0 to 119);
Clock : in STD_LOGIC;
ClockE : in STD_LOGIC);
end top;
architecture beh of top is
component CortexMacro is
Port ( MInputs : in STD_LOGIC_VECTOR (0 to 119);
MOutputs : out STD_LOGIC_VECTOR (0 to 119);
MCLK : in STD_LOGIC;
MCLKE : in STD_LOGIC;
VCC : in STD_LOGIC);
end component;
attribute LOC: string;
attribute LOC of Cortex: label is "SLICE_X12Y0";
attribute box_type : string;
attribute box_type of CortexMacro : component is "black_box";
begin
Cortex : component CortexMacro
port map (
MCLK => Clock,
MCLKE => ClockE,
MInputs => Inputs,
MOutputs => Outputs,
VCC => '1'
);
end beh;
The interesting thing is that if I create the hard macro using FPGA editor 9.2 then everything works like a charm.
As FPGA Editor 9.2 cannot open ISE 11.4 files I have to implement the hard macro using ISE 9.2 and as both versions of the ISE suit does not peacefully live on the same system I have a lot of trouble. I need to use the latest version for all the steps of the project.
Any ideas what has caused the fatal map crash? It looks like it comes from the power distibution and as you see at the end of the map report it has optimized XST_VCC. Could it be the source of the problem? Could it be because I named one of the inputs of the hardmacro "VCC" (providing GLOBAL_LOGIC1 to the HM logic)?
Cheers,
