When Virtex5 adds some outputs to another Virtex5, the result goes wrong

haihengcao · ‎12-26-2008

Hi,

We use Virtex5 to compress image data, and our design is like this: a first Virtex5(V1) receive data from sending board, do the comprssion and also transfer the original data to another Virtex5(V2) and the V2 do the compression too.

The V1 can always have the right result without the outputs to V2 but it goes wrong if it has the outputs to V2.

So what would the potential reasons for this problem?

awillen · ‎11-29-2007

How should we know? You give us hardly any information, and your question is confusing. Be more specific and post more details.

Signature:
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bassman59 · ‎02-25-2008

haihengcao wrote:

Hi,

We use Virtex5 to compress image data, and our design is like this: a first Virtex5(V1) receive data from sending board, do the comprssion and also transfer the original data to another Virtex5(V2) and the V2 do the compression too.

The V1 can always have the right result without the outputs to V2 but it goes wrong if it has the outputs to V2.

So what would the potential reasons for this problem?

Your design is screwed up.

Did you bother to simulate the entire board design, including both FPGAs, the source stimulus and the output data sink? If not, then your design hasn't been verified and debugging in-circuit as you are doing is a waste of time.

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