I am interesting in creating some tools to manipulate designs in the XDL file format.
I have used xdl -ncd2xdl to convert a design to XDL. Despite being "human readable," however, I am having quite a difficult time locating any documentation for the XDL format. Is there documentation of this format somewhere?
The XDL format gives output for nets like the following:
net "char_to_xmit<5>" ,
outpin "high4/V5_SingleSlice" B ,
inpin "uart/TxD_dataReg<7>" BX ,
pip CLBLM_X18Y100 M_B -> SITE_LOGIC_OUTS13 ,
pip CLBLM_X18Y94 SITE_BYP_B4 -> M_BX ,
pip INT_X18Y100 LOGIC_OUTS13 -> SL5BEG1 ,
pip INT_X18Y94 BYP4 -> BYP_B4 ,
pip INT_X18Y94 FAN2 -> FAN_BOUNCE2 ,
pip INT_X18Y94 FAN_BOUNCE2 -> BYP4 ,
pip INT_X18Y94 SE2MID1 -> FAN2 ,
pip INT_X18Y95 SL5END1 -> SE2BEG1 ,
;
I am interested in reconciling the various node names "SL5BEG1," etc with the names I see when I look at the design in FPGA editor. Does such documentation exist?
Thanks,
Ben
