Implementation

[gcqhyp]

   I want to configrate spartan6  XC6SLX75 with SPI flash W25Q64B, The interface make according to "Spartan-6 FPGA

Configuration User Guide " .The principle diagram as follows:

      But there is a problem that programming always fail,   what's more, the configration process is very slow and take about 7 minutes.

     I have checked M1,M0, CSO_B, SUSPEND, HSWAPEN,INIT_B. they are all work order during the configration. The CCLK output signal is about 12MHz.
   I use  iMPACT is 13.4 and 12.3.  Platform Cable USB II.  what wrong with my design? thanks!

[gcqhyp]

Supplement :I leave  the CFS and VBATT unconnected.

[eteam00]

There is no termination on the FPGA_CLK signal (CCLK output from the FPGA).  This might be a problem.  If you revise the board design, you should add a 33-ohm series termination resistor for this signal, near the FPGA (pin Y21).

• Does the FPGA configure reliably from JTAG?
• Can you reliably program the W25Q flash memory from JTAG (e.g. indirect programming using iMPACT) ?

From UG380 Figure 2-13:

1. The connection shown in Figure 2-13 uses the Winbond W25Q SPI series flash PROM. To enable the Quad output operation, the user must set the QE bit of the PROM’s status_reg[9] to 1 before the device can transmit in quad output mode, which is done at programming time in iMPACT software.
2. CCLK can be provided by the FPGA or an external clock source.
3. There are default pull-ups on the PROGRAM_B, INIT_B, and M0 pin.
4. Software support for x4 requires the x4 capability enabled in BitGen.
5. The SPI device needs to be programmed with a specific register setting, which can be done in iMPACT software, to enable x4 output.

From UG380 v2.3, page 43:

The Master SPI configuration mode in Spartan-6 FPGAs supports the Winbond W25Q Quad I/O SPI flash memory dual (x2) and quad bit (x4) memory read commands. To enable this configuration method in software, the BitGen spi_buswidth option is used to create a .bit file for SPI x2 or x4. The FPGA still initially boots in x1 mode and then switches to x2 or x4 mode.

 -- Bob Elkind

[gcqhyp]

      I am sure that I configure reliably from JTAG and program the W25Q flash memory from JTAG whith indirect programming.  Today I changed the CCLK connection, as follow:

  But It was to no avail.

   According to your advice, Is the CCLK connection revised like this?

     

Add a current-limiting resistance???

    I have paid attention to the QE bit,  but I do not set the QE bit of the PROM’s status_reg[9] to 1. I do not know how to do it.in iMPACT 13.4 software. Can you tell me detailed process? 

Thanks very much.

[eteam00 · Accepted solution]

Add a current-limiting resistance???

A series termination resistor serves to match impedance to the circuit board trace to avoid ringing and control undesired reflections.  It is not a current limit.  33-ohms is a good value.

If you continue with board design and development work, you need to learn transmission line principles, concepts, and practices.  The best source of such instruction is an experienced board designer.  The book from which I first learned transmission line principles is the MECL System Design Handbook, by William R Blood.  This book is out of print, but used copies are available for purchase.

I have paid attention to the QE bit,  but I do not set the QE bit of the PROM’s status_reg[9] to 1. I do not know how to do it.in iMPACT 13.4 software. Can you tell me detailed process?

Right-click on Generate Programming File, select Process Properties in pop-up menu.

Select Configuration Options, and set the SPI Configuration Bus Width option.

You will need to re-generate the bitfile and re-program the SPI flash memory.

-- Bob Elkind

[gcqhyp]

Thanks

[gcqhyp]

        Thank you for your help, Now I can configrate it successfully. But The time is too long for spartan6 configration. it takes 956 sec to configrate. My code is only to  implement that one port receive a signal and other one output this signal. 

      I want to know  what factors are influence the time. thanks.  

     The Platform Cable USB II configuration clock (TCK_CCLK_SCK) frequency is  set 12MHz and  configration rate is 4Mbit/s during the configration.

[eteam00]

Please clarify:

• What operation or process completes in 956 seconds?
• How are you measuring the elapsed time of this process?
• What BitGen setting are you using for Startup Options?
• What BitGen setting are you using for Configuration Options?
• What BitGen setting are you using for General Options?
• What BitGen setting are you using for Encryption Options?

-- Bob Elkind

[gcqhyp]

1. the process include erasing, programming and verifying the spi flash W25Q64B.

2. General Options : 

     Enable: Run Design Rules Checker (DRC)

    Create Bit File

     Enable Cyclic Redundancy Checking (CRC)

3. General Options:

     Configration Rate is 16Mbit/s

     Spi buswidth is 4

    Others keep default

4.Startup Options

    StartUpClk: CCLK

    Others keep default

5. Encryption Options:

     I do not use it.

[eteam00]

1. the process include erasing, programming and verifying the spi flash W25Q64B.

What you describe are iMPACT/JTAG programming (and indirect programming) operations, not self-configuration.  Most (and maybe all) the BitGen settings will not affect the flash memory programming time.

Yes, it is slow and tedious.  The good news is that you use these function only during development and debugging.

-- Bob Elkind