Implementation

[rikraf]

Hi all,

I have a design which I'm migrating from Virtex5 (SX50T) to Virtex6 (CX130T).  I've been bogged down for several days over the fact that the design takes about 10 hours to map, where it used to take 30 min in the old device (though the new one is 4x bigger).  I've narrowed it down to the following:

I have a divider core generated with Divider Generator v3.0.  I regenerated the core for the V6, but when MAP gets to phase 10.8 it just hangs up.  This is true even when I instantiate just thedivider and nothing else.  Divider Generator 3.0 is supposed to support V6, but something is wrong.

I could use Divder Generator v4.0 I suppose, but the ports are all different.

Any ideas appreciated.

Thanks,

Rick

[rikraf · Accepted solution]

I discovered the problem here.  The 10-hour mapping occurs when I used Divider Generator 3.0 with the Virtex6 device IF I selected the Radix-2, 1 clock per result, implementation.  If I changed to either "High Radix" or 2 clocks per result, the mapping finished in a minute.

Hope that helps somebody else.

Rick

[franchute]

I know this post is old, but I needed to thank you for solving it. I've been trying to solve this for days. I even wrote again my modules sharing only 1 divider to see if that could be mapped by the ISE.

I'm working with a Spartan6 , so for Spartan6 user this post is valid to!

Thnx
Regards

[bassman59]

---

rikraf wrote:

I discovered the problem here.  The 10-hour mapping occurs when I used Divider Generator 3.0 with the Virtex6 device IF I selected the Radix-2, 1 clock per result, implementation.  If I changed to either "High Radix" or 2 clocks per result, the mapping finished in a minute.

Hope that helps somebody else.

Rick

---

Sounds like it was trying to fit a large combinatorial block and make it meet timing. Adding the second register pipelined the divider, so the tools are more easily able to make it work.

[gbredthauer]

I've run into the same problem.  A Divider Generator 3.0 that worked on a Virtex 5 took > 10 hours to map on a Virtex 6.  I'm running ISE 13.2.  Divider settings: radix2, 32 bit dividend/quotient, 16 bit divisor, 16 bit fractional remainder, unsigned, 1 clock per division.  I verified this bug by instantiating the divider alone in a fresh XC6VLX75T project.  Divider Generator 4.0 has the same problem.  Switching to 2 clocks per division fixes it (but breaks my exisiting designs).  I'm downloading ISE 14.2 now to see if the bug still exists.

-Greg

[gbredthauer]

The bug still exists in ISE 14.2. Changing the target device to a Virtex 5 also solves the problem. I've opened a web case to try to squash this particular bug.

[gbredthauer]

The result of the webcase was that this is indeed a bug in the tools.  It's been flagged to be corrected in a future ISE version.