Implementation

[jesicabenani]

I got error when implementing the design. there is error of mapping no 116 & 52. i can't found any solution for that.

[rcingham]

Which FPGA?
What version of ISE?
Post the entire error messages.

[jesicabenani]

fpga kit:spartan3E

ISE version:11.1

[joelby]

Are you able to share the exact, complete error message? And a complete, minimum code example that causes the errors?

[jesicabenani]

I have an error of mapping:

no52:Problem encountered processing RPMs

no116:The design is empty,no process will be done.

[joelby]

Can you provide a complete, minimum code example that causes the errors?

[jheslip]

jesicabenani 

The people on the forum are trying to help you around this issue, you need to provide as much information as possible so they can understand the issue, giving just the error numbers does not help at a minimum you need to provide the full error message otherwise it will be difficult to assist.

[bwade]

The Map:52 error has to do with an RPM macro attribute causing a problem.

The Map:116 error "The design is empty" indicates that the entire design has been removed by trimming. You can either examine the trimming section of the .mrp file to see where the trimming started or if you know the design is incomplete, disable trimming with the map -u option. More about trimming here:

http://www.xilinx.com/support/answers/23990.htm