Implementation

[boneswu]

Hi,

I use the same design to do implementation in V6 and V5.

Its utilization is lesser than 50% in V6, and more than 90% in V5.

However, the implementation time in V6 is more 2X than V5.

Is it normal?

I don't change any macro definition in coregen to V6 from V5.

Is it the cause?

Thanks!!

[boneswu]

Hi,

I use ISE 12.1.

V6 device is XC6VLX760-FF1760.

V5 device is XC5VLX330-FF1760.

Thanks!!

[shantesh]

What phase of the implementation takes longer? (I'm guessing its the mapper) Did you try comparing the report files for the two builds?

[shantesh]

Also, ideally you should be regenerating your cores

[boneswu]

Hi, shantesh,

The PAR time is too long and fail to meet all hold time violations.

The same design can meet in 2 VIRTEX-5, and I just merge them into single VIRTEX-6.

It doesn't show any error except routing congestion and result hold time violation.

Thanks!!

[bwade]

There have been some improvements wrt hold time issues for 13.1. You should give 13.1 a try if you haven't already. I'd also suggest that you check your clock paths for the clocks involved in the hold errors to see if there is an unusual amount of delay or skew. There's a clock summary near the end of the .par log file that will provide this information.

[linhu]

Can your design in V6 LX760 meet timing? If can't meet timing, the implementation time will be very long

[linhu]

If your design in V6 LX760 has issue in routing, p lease check the WP381: Virtex-6 FPGA Routing Optimization
Design Techniques.  You can download it from xilinx website