Implementation

[applefat]

I created another circuit, even more basic. It's just a single LUT with an input and an output. When I try to instantiate this, I get the following:

ERROR:Place:835 - Given the original pre-placement, no legal placements can be
   found for 1 group(s). The following is the description of these group(s). The
   relative offsets of the components are shown in brackets next to the
   component names.
        LUT puf3/Q_OBUF (0, 0)
        LUT puf3/Q_OBUF (0, 0)
        LUT puf3/Q_OBUF (0, 0)
        LUT puf3/Q_OBUF (0, 0)
        LUT puf3/Q_OBUF (0, 0)
        LUT puf3/Q_OBUF (0, 0)
        LUT puf3/Q_OBUF (0, 0)
        LUT puf3/Q_OBUF (0, 0)
        FF puf3/Q_OBUF (0, 0)
        FF puf3/Q_OBUF (0, 0)
        FF puf3/Q_OBUF (0, 0)
        FF puf3/Q_OBUF (0, 0)
        FF puf3/Q_OBUF (0, 0)
        FF puf3/Q_OBUF (0, 0)
        FF puf3/Q_OBUF (0, 0)
        FF puf3/Q_OBUF (0, 0)


My code for the entire macro is below:

entity top is
    port(
        x: in std_logic;
        q: out std_logic
        );
end top;

architecture Behavioral of top is

    signal t: std_logic;

    attribute lock_pins: string;
    attribute lock_pins of tri2 : label is "all";


begin

tri2 : LUT5
generic map (
INIT => X"55555555") -- Specify LUT Contents
port map (
O => t, -- LUT general output
I0 => x, -- LUT input
I1 => '0', -- LUT input
I2 => '0', -- LUT input
I3 => '0', -- LUT input
I4 => '0' -- LUT input
);

q<=t;

end Behavioral;

[bwade]

Are you setting the slice as the reference comp? Can you attach the macro along with your other source in a zip file?

[applefat]

I did set that.

Attached is a project for my target device. It is the simplest test I can think of, but it also did not synthesize.

Three important files:

top.vhd--file that instanciates the macro

puftest.vhd--file from which the macro was created

puftest.nmc--the macro file I created

Thanks bwade for taking a look.

[bwade · Accepted solution]

I used your existing NGC and NMC files and I was able to get this to work by adding a UCF LOC constraint:

INST i0 LOC =SLICE_X0Y2;

I was also able to place the macro manually in FPGA Editor. The bug is just that auto-placement can't handle the macro. I see that you never defined a reference comp for the macro. That doesn't seem to matter for this single component case. For a larger macro you'll probably need to do that to LOC it successfully

[applefat]

Ah yeah, it works now, it was just the missing LOC. In retrospect, it's clear why that should be necessary, especially for very large macros. If it's essential though, in the future maybe a note should be added to the Xilinx reference page, for others....

One last question. I did set the reference comp in fpga_editor. Is there a code constraint you were looking for?

Thanks a lot for your help!

[bwade]

You define the reference comp in the editor. A circle will then appear in that comp. Maybe you just didn't save that version. There's no reason the placer can't handle the macro. I've filed a CR for the placer bug.