mapping error in ISE12.2 for GTP GTPCLKOUT

liangr · ‎12-22-2009

Hi all, I am now coming to the mapping step and I have assign the ports to the local nets. The circuit is translated successfully but then here comes the buffer problems. I am new to the design flow so I am not sure where I should added buffers and how it can be added.

The original message is listed below:

*********************************************************************************************************

Started : "Map".
Running map...
Command Line: map -intstyle ise -p xc6slx45t-fgg484-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc area -power off -o GTP_top_map.ncd GTP_top.ngd GTP_top.pcf
Using target part "6slx45tfgg484-3".
Mapping design into LUTs...
ERROR:LIT:543 - GTPA1_DUAL symbol
   "GTP_CORE_inst/tile0_gtp_core_wimax_i/gtpa1_dual_i" has buses GTPCLKOUT0 or
   GTPCLKOUT1 driving a block other than a BUFIO2. These buses have dedicated
   routes to BUFIO2 buffers. BUFIO2 buffers need to be inserted in between these
   pins of GTPA1_DUAL and their loads. Please modify your design to avoid this
   unroutable situation.
Errors found during logical drc.

Design Summary
--------------
Number of errors : 1
Number of warnings : 0

Process "Map" failed

***************************************************************************************************

According to ug382, I know the buffer IOs so should I add it manually or just choose some opitions to realize it?

kka · ‎12-02-2009

If you are using GTPCLKOUT0 or GTPCLKOUT1 to drive your fabric logic, you should use BUFIO2 to buffer the signal.

This requirement is applicable only for Spartan-6 device unlike other family devices use BUFG in general.

zhong0920 · ‎02-22-2011

Problem is: even if a BUFIO2 is inserted between the GTPCLKOUT and a PLL, the tool will still complain about the two clocking resources not LOCed so that it is not able to place them. See the thing is, GTP is connected to fixed TX/RX, and REFCLK pins, so GTP itself is in fact "LOCed". If you put a BUFIO2 behind it, according to clocking resource guide, BUFIO2s are dedicated to GTPs, so they are "LOCed" too. The complaint about BUFIO2 being un-LOCed is not valid. I was wondering whether this was a bug in the tool itself, and hoping that this could be clarified.

Thank you!

jindp · ‎07-02-2012

I have met the same problem in ISE13.2. I design the GTP User Clock as the illustration on page 139 of UG386, but,

during "map" step, the error occurs "ERROR:Place:1286 - Placer has detected a BUFIO2 component <
   GTP245_267_map/GTP267_TXUSRCLK_GEN0/CLKIN_BUFIO2_GENERATION > driving
   component < GTP245_267_map/GTP267_TXUSRCLK_GEN0/PLL_DCM_MAP > (on pin < CLKIN
   >) which is not associated with an IOB component. Automatic clock placement
   of components not associated with an IOB is not supported. If the load
   component is an IODELAY, the user can LOC the IODELAY and BUFIO2 to the same
   half-bank and re-run placer."

I use the GTPCLKOUT as the reference clock.

Who can explain something? Sincerely.