Implementation

[vadimh]

Hi,

I have the following in my design problem:
I need a total of 6 different clock frequencies, which I can only create by using PLLs and I did. I use the ML505 board with a XC5VLX50T and the clock frequencies that I need to reach me only if I use 3 of the 6 included PLLs. I use a high reference clock with which I create two frequencies in a PLL. In the other two PLLs I want to create using an output frequency of the first PLL to the other four frequencies. I made my design synthesis capability and that has worked quite well in the end. But during the translation process, I keep getting the following error messages and do not know what to do:

ERROR:NgdBuild:770 - IBUFG 'clock2/CLKIN1_IBUFG_INST' and BUFG
   'clock/CLKOUT1_BUFG_INST' on net 'clk_out_OBUF' are lined up in series.
   Buffers of the same direction cannot be placed in series.
ERROR:NgdBuild:462 - input pad net 'clk_out_OBUF' drives multiple buffers:
     pin I on block clock2/CLKIN1_IBUFG_INST with type IBUFG,
     pin I on block clock3/CLKIN1_IBUFG_INST with type IBUFG,
     pin I on block clk_out_OBUF with type OBUF
ERROR:NgdBuild:924 - input pad net 'clk_out_OBUF' is driving non-buffer
   primitives:
     pin O on block clock/CLKOUT1_BUFG_INST with type BUFG
ERROR:NgdBuild:947 - input pad net 'clk_out_OBUF' is driving non-input
   buffer(s):
     pin O on block clock/CLKOUT1_BUFG_INST with type BUFG

I've also done out of necessity the output clock of the first PLL, which I use as a reference clock fed by a register and then forwarded to all the PLL to become independent. But I'm just not progressing.
The synthesis takes a long time so I would be glad if someone could quickly as possible to describe the appropriate reference to the solution of this problem. I thank you in advance for the answers.

[awillen]

Hello vadimh,

posting the code that produces the errors couldn't hurt.

Have you used the output of a IBUFG as input to a BUFG? That would explain the first error message. But as I said, posting the code would help a lot.

Adrian

[vadimh]

Hello awillen,

Yes I must do, since I need quite crooked values as clock frequencies.
For reference, I use the 200 MHz PLL, which are available on the board. From this I generate in the first PLL clock frequency of 13.904 MHz and 27.808 MHz. I need 6.952 MHz so I share the first frequency by 2 The 27.808 MHz which I will also need, I use as a reference for PLL 2 and PLL3. In this I generate clock frequencies to 3.476 MHz, 4.345 MHz, 5.214 MHz and 6.083 MHz. The whole I have made over the Core Generator, classically on the set-up function PLL_ADV, so I think it does not really help further if I was already making the Core Generator to post here already.
But once I post the function calls that I call the PLL functions of the Core Generator:

dvb_c_clk clock(.CLKIN1_N_IN(ref_clk_n),            //200MHz Reference clock negativ
                             .CLKIN1_P_IN(ref_clk_p),            //200MHz Reference clock positiv    
                             .RST_IN(reset),                        
                             .CLKOUT0_OUT(clk_up),                 //13.904MHz 2*baseband symbol clock
                             .CLKOUT1_OUT(samp_clk));            //27.808MHz upsampled clock
        
        dvb_c_clk_qam1632 clock2(.CLKIN1_IN(samp_clk),    //27.808MHz reference clock from PLL1
                                         .RST_IN(reset),
                                         .CLKOUT0_OUT(clk_si16),    //3.476MHz clock for 16qam
                                         .CLKOUT1_OUT(clk_si32));     //4.345MHz clock for 32qam
        
        dvb_c_clk_qam64128 clock3(.CLKIN1_IN(samp_clk),    //27.808MHz reference clock from PLL1
                                         .RST_IN(reset),
                                         .CLKOUT0_OUT(clk_si64), //5.214MHz clock for 64qam
                                         .CLKOUT1_OUT(clk_si128)); //6.083MHz clock for 128qam