Implementation

[acr4]

Recently, PAR has been displaying the message "TASK FINISHED WITH 1 ERRORS".

This occurs one or two times, between Phase 3 and 4.  The design is never fully routed until Phase 5.  My design is able to close timing (well, close enough!) and fully route.

The occurance of this message is pretty recent, although I have been unable to isolate the cause.  Google-search and forum-search haven' t helped yet either (although I may just be doing it wrong!)

I am using 64-bit ISE 13.2 on Linux, and building on a V6 LX550T with lots of internally-generated clock domains, lots of GTX ports, and fairly aggressive floor-planning.

Occasionally I also get a WARNING:Place:913 during MAP, which seems to also be a fairily new message.  Analyzing the design in planAhead w/ an EDIF and fully-routed NCD shows that no nets route through the SLICE referenced in the warning message, so I'm having little luck there too, but I figured it was worth mentioning since the MAP and PAR messages may be related.

Has anyone seen this obscure PAR message?  Should I spend any more time tracking it down or is it one of the obscure and harmless messages that PAR barfs sometimes (like 'pin bounce' message)?

Thanks,

-acr4

[bwade · Accepted solution]

It's related to the multi-threading feature and is thought to be harmless. A CR is assigned to be fixed in 14.1.

[acr4]

Cool, thanks bwade!

-acr4

[chethan.ananth]

I am using ISE 13.4 and get the same error right after Phase 2 of PAR. I see this happening only when I instantiate a chipscope ICON and ILA core in the design. PAR fails and reports significant timing violations. I have used the same design with chipscope in earlier versions of ISE and have had no problems using chipscope.

Any suggestions please?