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05-10-2012 11:43 PM
Hi, everyone
I'm using ML605 Evaluation Board to do my project and now I encountered a problem, call for help!!
When the project goes to translate process, it pops out these warnings
such as
"WARNING:ConstraintSystem:203 - A target design object for the Locate constraint
'<INST: UniqueName:
/EncoderTop/EXPANDED/EncoderTop/soft_enc_i\/embd_s
/DDR3_SDRAM\/mpmc_core_0\/gen_v6_ddr3_phy.mpmc_phy
clk_gen\/gen_loop_col0.u_...>' could not be found and so the Locate
constraint will be removed.
WARNING:ConstraintSystem:203 - A target design object for the Locate constraint
'<INST: UniqueName:
/EncoderTop/EXPANDED/EncoderTop/soft_enc_i\/embd_s
/DDR3_SDRAM\/mpmc_core_0\/gen_v6_ddr3_phy.mpmc_phy
clk_gen\/gen_loop_col1.u_...>' could not be found and so the Locate
constraint will be removed.
" and etc
It seems that those locate constraint didn't work.
Here is my Project Hierarchy
EncoderTop/soft_enc_i/embd_stub/embd_system/....
Hopefully Somebody could help me?
Thanks
songxin
And my EncoderTop.ucf is like this
// UCF FILE
# Encoder Top
NET sys_clk_in_p LOC = J9 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE;
NET sys_clk_in_n LOC = H9 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE;
Net sys_rst_pin PULLUP;
Net sys_rst_pin LOC= H10 | IOSTANDARD=SSTL15;
## System level constraints
Net sys_rst_pin TIG;
Net sys_clk_in_p TNM_NET = dcm_clk_s;
TIMESPEC TS_dcm_clk_s = PERIOD dcm_clk_s 5000 ps;
Net sys_rst_pin TIG;
## adding by rong
NET "sys_rst_pin" CLOCK_DEDICATED_ROUTE = FALSE;
## IO Devices constraints
#### Module RS232_Uart_1 constraints
Net fpga_0_RS232_Uart_1_sin_pin LOC=J24 | IOSTANDARD=LVCMOS25;
Net fpga_0_RS232_Uart_1_sout_pin LOC=J25 | IOSTANDARD=LVCMOS25;
#### Module LEDs_8Bit constraints
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<0> LOC = AC22;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<1> LOC = AC24;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<2> LOC = AE22;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<3> LOC = AE23;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<4> LOC = AB23;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<5> LOC = AG23;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<6> LOC = AE24;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<7> LOC = AD24;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<*> IOSTANDARD=LVCMOS25;
#### Module LEDs_Positions_GPIO constraints
Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> LOC=AP24;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> LOC=AD21;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> LOC=AH28;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> LOC=AE21;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> LOC=AH27;
Net fpga_0_LEDs_Positions_GPIO_IO_pin<*> IOSTANDARD=LVCMOS15;
#### Module Push_Buttons_GPIO constraints
#GPIO PB Center
Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<0> LOC = G26;
#GPIO PB West
Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<1> LOC = H17;
#GPIO PB South
Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<2> LOC = A18;
#GPIO PB East
Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<3> LOC = G17;
#GPIO PB North
Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<4> LOC = A19;
Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<*> IOSTANDARD=SSTL15_T_DCI;
#### Module SysACE_CompactFlash constraints
#### Module DIP_Switches_4Bit constraints
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_I_pin<0> LOC=D22;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_I_pin<1> LOC=C22;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_I_pin<2> LOC=L21;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_I_pin<3> LOC=L20;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_I_pin<4> LOC=C18;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_I_pin<5> LOC=B18;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_I_pin<6> LOC=K22;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_I_pin<7> LOC=K21;
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_I_pin<*> IOSTANDARD = SSTL15;
##################################################
# Temporary Constraints
##################################################
# Leave here until we cleanup reset timing
disable = reg_sr_o;
disable = reg_sr_r;
# Constrain BUFR clocks used to synchronize data from IOB to fabric logic
# Note that ISE cannot infer this from other PERIOD constraints because
# of the use of OSERDES blocks in the BUFR clock generation path
NET "*/*phy_if_0/clk_rsync[*]" TNM_NET = TNM_clk_rsync;
TIMESPEC TS_clk_rsync = PERIOD "TNM_clk_rsync" 5000 ps;
# Signal to select between controller and physical layer signals. Four divided by two clock
# cycles (8 memory clock cycles) are provided by design for the signal to settle down.
# Used only by the phy modules.
INST "*/u_phy_init/u_ff_phy_init_data_sel" TNM = "TNM_PHY_INIT_SEL";
TIMESPEC "TS_MC_PHY_INIT_SEL" = FROM "TNM_PHY_INIT_SEL" TO FFS = 20000 ps; // mem clock period * 8 or Clk0 period * 4
##################################################
# DDR3/Status signals
##################################################
NET "fpga_0_DDR3_SDRAM_DDR3_DQ_pin[*]"
NET "fpga_0_DDR3_SDRAM_DDR3_Addr_pin[*]"
NET "fpga_0_DDR3_SDRAM_DDR3_BankAddr_pin[*]"
NET "fpga_0_DDR3_SDRAM_DDR3_RAS_n_pin"
NET "fpga_0_DDR3_SDRAM_DDR3_CAS_n_pin"
NET "fpga_0_DDR3_SDRAM_DDR3_WE_n_pin"
NET "fpga_0_DDR3_SDRAM_DDR3_Reset_n_pin"
NET "fpga_0_DDR3_SDRAM_DDR3_CS_n_pin[*]"
NET "fpga_0_DDR3_SDRAM_DDR3_ODT_pin[*]"
NET "fpga_0_DDR3_SDRAM_DDR3_CE_pin[*]"
NET "fpga_0_DDR3_SDRAM_DDR3_DM_pin[*]"
NET "fpga_0_DDR3_SDRAM_DDR3_DQS_pin[*]"
NET "fpga_0_DDR3_SDRAM_DDR3_DQS_n_pin[*]"
NET "fpga_0_DDR3_SDRAM_DDR3_Clk_pin[*]"
NET "fpga_0_DDR3_SDRAM_DDR3_Clk_n_pin[*]"
##################################################
# Location Constraints
##################################################
# Banks specified in the comments may no longer be valid
NET "fpga_0_DDR3_SDRAM_DDR3_DQ_pin[0]"
NET "fpga_0_DDR3_SDRAM_DDR3_DQ_pin[1]"
NET "fpga_0_DDR3_SDRAM_DDR3_DQ_pin[2]"
NET "fpga_0_DDR3_SDRAM_DDR3_DQ_pin[3]"
NET "fpga_0_DDR3_SDRAM_DDR3_DQ_pin[4]"
NET "fpga_0_DDR3_SDRAM_DDR3_DQ_pin[5]"
NET "fpga_0_DDR3_SDRAM_DDR3_DQ_pin[6]"
NET "fpga_0_DDR3_SDRAM_DDR3_DQ_pin[7]"
NET "fpga_0_DDR3_SDRAM_DDR3_DQ_pin[8]"
NET "fpga_0_DDR3_SDRAM_DDR3_DQ_pin[9]"
NET "fpga_0_DDR3_SDRAM_DDR3_DQ_pin[10]"
NET "fpga_0_DDR3_SDRAM_DDR3_DQ_pin[11]"
NET "fpga_0_DDR3_SDRAM_DDR3_DQ_pin[12]"
NET "fpga_0_DDR3_SDRAM_DDR3_DQ_pin[13]"
NET "fpga_0_DDR3_SDRAM_DDR3_DQ_pin[14]"
NET "fpga_0_DDR3_SDRAM_DDR3_DQ_pin[15]"
NET "fpga_0_DDR3_SDRAM_DDR3_DQ_pin[16]"
NET "fpga_0_DDR3_SDRAM_DDR3_DQ_pin[17]"
NET "fpga_0_DDR3_SDRAM_DDR3_DQ_pin[18]"
NET "fpga_0_DDR3_SDRAM_DDR3_DQ_pin[19]"
NET "fpga_0_DDR3_SDRAM_DDR3_DQ_pin[20]"
NET "fpga_0_DDR3_SDRAM_DDR3_DQ_pin[21]"
NET "fpga_0_DDR3_SDRAM_DDR3_DQ_pin[22]"
NET "fpga_0_DDR3_SDRAM_DDR3_DQ_pin[23]"
NET "fpga_0_DDR3_SDRAM_DDR3_DQ_pin[24]"
NET "fpga_0_DDR3_SDRAM_DDR3_DQ_pin[25]"
NET "fpga_0_DDR3_SDRAM_DDR3_DQ_pin[26]"
NET "fpga_0_DDR3_SDRAM_DDR3_DQ_pin[27]"
NET "fpga_0_DDR3_SDRAM_DDR3_DQ_pin[28]"
NET "fpga_0_DDR3_SDRAM_DDR3_DQ_pin[29]"
NET "fpga_0_DDR3_SDRAM_DDR3_DQ_pin[30]"
NET "fpga_0_DDR3_SDRAM_DDR3_DQ_pin[31]"
NET "fpga_0_DDR3_SDRAM_DDR3_Addr_pin[12]"
NET "fpga_0_DDR3_SDRAM_DDR3_Addr_pin[11]"
NET "fpga_0_DDR3_SDRAM_DDR3_Addr_pin[10]"
NET "fpga_0_DDR3_SDRAM_DDR3_Addr_pin[9]"
NET "fpga_0_DDR3_SDRAM_DDR3_Addr_pin[8]"
NET "fpga_0_DDR3_SDRAM_DDR3_Addr_pin[7]"
NET "fpga_0_DDR3_SDRAM_DDR3_Addr_pin[6]"
NET "fpga_0_DDR3_SDRAM_DDR3_Addr_pin[5]"
NET "fpga_0_DDR3_SDRAM_DDR3_Addr_pin[4]"
NET "fpga_0_DDR3_SDRAM_DDR3_Addr_pin[3]"
NET "fpga_0_DDR3_SDRAM_DDR3_Addr_pin[2]"
NET "fpga_0_DDR3_SDRAM_DDR3_Addr_pin[1]"
NET "fpga_0_DDR3_SDRAM_DDR3_Addr_pin[0]"
NET "fpga_0_DDR3_SDRAM_DDR3_BankAddr_pin[2]"
NET "fpga_0_DDR3_SDRAM_DDR3_BankAddr_pin[1]"
NET "fpga_0_DDR3_SDRAM_DDR3_BankAddr_pin[0]"
NET "fpga_0_DDR3_SDRAM_DDR3_RAS_n_pin"
NET "fpga_0_DDR3_SDRAM_DDR3_CAS_n_pin"
NET "fpga_0_DDR3_SDRAM_DDR3_WE_n_pin"
NET "fpga_0_DDR3_SDRAM_DDR3_Reset_n_pin"
NET "fpga_0_DDR3_SDRAM_DDR3_CS_n_pin[0]"
NET "fpga_0_DDR3_SDRAM_DDR3_ODT_pin[0]"
NET "fpga_0_DDR3_SDRAM_DDR3_CE_pin[0]"
NET "fpga_0_DDR3_SDRAM_DDR3_DM_pin[0]"
NET "fpga_0_DDR3_SDRAM_DDR3_DM_pin[1]"
NET "fpga_0_DDR3_SDRAM_DDR3_DM_pin[2]"
NET "fpga_0_DDR3_SDRAM_DDR3_DM_pin[3]"
NET "fpga_0_DDR3_SDRAM_DDR3_DQS_pin[0]"
NET "fpga_0_DDR3_SDRAM_DDR3_DQS_n_pin[0]"
NET "fpga_0_DDR3_SDRAM_DDR3_DQS_pin[1]"
NET "fpga_0_DDR3_SDRAM_DDR3_DQS_n_pin[1]"
NET "fpga_0_DDR3_SDRAM_DDR3_DQS_pin[2]"
NET "fpga_0_DDR3_SDRAM_DDR3_DQS_n_pin[2]"
NET "fpga_0_DDR3_SDRAM_DDR3_DQS_pin[3]"
NET "fpga_0_DDR3_SDRAM_DDR3_DQS_n_pin[3]"
NET "fpga_0_DDR3_SDRAM_DDR3_Clk_pin[0]"
NET "fpga_0_DDR3_SDRAM_DDR3_Clk_n_pin[0]"
##################################################
# MMCM Location Constraints
##################################################
# modified by rong
#INST "clock_generator_0/clock_generator_0/Using_MMCM0.M
INST "*/clock_generator_0/clock_generator_0/Using_MMCM0
######
INST "*/u_mmcm_clk_base" LOC = "MMCM_ADV_X0Y8";
##################################################
# Capture Clock Constraints
# Available sites are:
# Bank 35:
# C13: IO_L11P_SRCC_35 : X2Y137 : CPT[0]
# M12: IO_L10P_MRCC_35 : X2Y139 : RSYNC[0]
# L13: IO_L9P_MRCC_35 : X2Y141 : CPT[1]
# K14: IO_L8P_SRCC_35 : X2Y143 : CPT[2]
# Bank 26:
# F21: IO_L10P_MRCC_26 : X1Y179 : CPT[3]
# B20: IO_L9P_MRCC_26 : X1Y181 : CPT[4]
# F19: IO_L8P_SRCC_26 : X1Y183 :
# Bank 25:
# F25: IO_L11P_SRCC_25 : X1Y137 : CPT[5]
# C29: IO_L10P_MRCC_25 : X1Y139 : RSYNC[1]
# C28: IO_L9P_MRCC_25 : X1Y141 : CPT[6]
# D24: IO_L8P_SRCC_25 : X1Y143 : CPT[7]
##################################################
##################################################
# Place RSYNC OSERDES and IODELAY:
##################################################
# CLK_RSYNC[0]: Site M12
INST "*/u_phy_rdclk_gen/gen_loop_col0.u_oserdes_rsync"
LOC = "OLOGIC_X2Y139";
INST "*/u_phy_rdclk_gen/gen_loop_col0.u_odelay_rsync"
LOC = "IODELAY_X2Y139";
INST "*/u_phy_rdclk_gen/gen_loop_col0.u_bufr_rsync"
LOC = "BUFR_X2Y6";
# CLK_RSYNC[1]: Site C29
INST "*/u_phy_rdclk_gen/gen_loop_col1.u_oserdes_rsync"
LOC = "OLOGIC_X1Y139";
INST "*/u_phy_rdclk_gen/gen_loop_col1.u_odelay_rsync"
LOC = "IODELAY_X1Y139";
INST "*/u_phy_rdclk_gen/gen_loop_col1.u_bufr_rsync"
LOC = "BUFR_X1Y6";
# Place CPT OSERDES and IODELAY:
# DQS[0]: Site C13
INST "*/u_phy_rdclk_gen/gen_ck_cpt[0].u_oserdes_cpt"
LOC = "OLOGIC_X2Y137";
INST "*/u_phy_rdclk_gen/gen_ck_cpt[0].u_odelay_cpt"
LOC = "IODELAY_X2Y137";
# DQS[1]: Site L13
INST "*/u_phy_rdclk_gen/gen_ck_cpt[1].u_oserdes_cpt"
LOC = "OLOGIC_X2Y141";
INST "*/u_phy_rdclk_gen/gen_ck_cpt[1].u_odelay_cpt"
LOC = "IODELAY_X2Y141";
# DQS[2]: Site K14
INST "*/u_phy_rdclk_gen/gen_ck_cpt[2].u_oserdes_cpt"
LOC = "OLOGIC_X2Y143";
INST "*/u_phy_rdclk_gen/gen_ck_cpt[2].u_odelay_cpt"
LOC = "IODELAY_X2Y143";
# DQS[3]: Site F25
INST "*/u_phy_rdclk_gen/gen_ck_cpt[3].u_oserdes_cpt"
LOC = "OLOGIC_X1Y137";
INST "*/u_phy_rdclk_gen/gen_ck_cpt[3].u_odelay_cpt"
LOC = "IODELAY_X1Y137";
##################################################
# OCB Monitor Constraints
##################################################
# Site J10
INST "*/gen_enable_ocb_mon.u_phy_ocb_mon_top/u_oserdes_
LOC = "OLOGIC_X2Y130";
##################################################
# DCI Cascading
##################################################
CONFIG DCI_CASCADE = "26 25";
CONFIG DCI_CASCADE = "36 35";
##################################################
# Debug Constraints
##################################################
# Temporary workaround to prevent tools from performing timing analysis on
# ck_p/ck_n feedback path through the MMCM to the MMCM.LOCK signal (which in
# turn is in reset logic within the CLB fabric). This analysis is not
# necessary because the MMCM.LOCK signal is synchronized to the BUFG clock
# before being used.
NET "fpga_0_DDR3_SDRAM_DDR3_Clk_pin[*]" TIG;
NET "fpga_0_DDR3_SDRAM_DDR3_Clk_n_pin[*]" TIG;
#### Module Hard_Ethernet_MAC constraints
Net fpga_0_Hard_Ethernet_MAC_TemacPhy_RST_n_pin LOC=AH13;
Net fpga_0_Hard_Ethernet_MAC_TemacPhy_RST_n_pin IOSTANDARD = LVCMOS25;
Net fpga_0_Hard_Ethernet_MAC_TemacPhy_RST_n_pin TIG;
Net fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin<0> LOC=AM11;
Net fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin<0> IOSTANDARD = LVCMOS25;
Net fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin<1> LOC=AL11;
Net fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin<1> IOSTANDARD = LVCMOS25;
Net fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin<2> LOC=AG10;
Net fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin<2> IOSTANDARD = LVCMOS25;
Net fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin<3> LOC=AG11;
Net fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin<3> IOSTANDARD = LVCMOS25;
Net fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin<4> LOC=AL10;
Net fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin<4> IOSTANDARD = LVCMOS25;
Net fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin<5> LOC=AM10;
Net fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin<5> IOSTANDARD = LVCMOS25;
Net fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin<6> LOC=AE11;
Net fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin<6> IOSTANDARD = LVCMOS25;
Net fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin<7> LOC=AF11;
Net fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin<7> IOSTANDARD = LVCMOS25;
Net fpga_0_Hard_Ethernet_MAC_GMII_TX_EN_0_pin LOC=AJ10;
Net fpga_0_Hard_Ethernet_MAC_GMII_TX_EN_0_pin IOSTANDARD = LVCMOS25;
Net fpga_0_Hard_Ethernet_MAC_GMII_TX_ER_0_pin LOC=AH10;
Net fpga_0_Hard_Ethernet_MAC_GMII_TX_ER_0_pin IOSTANDARD = LVCMOS25;
Net fpga_0_Hard_Ethernet_MAC_GMII_TX_CLK_0_pin LOC=AH12;
Net fpga_0_Hard_Ethernet_MAC_GMII_TX_CLK_0_pin IOSTANDARD = LVCMOS25;
Net fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin<0> LOC=AN13;
Net fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin<0> IOSTANDARD = LVCMOS25;
Net fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin<1> LOC=AF14;
Net fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin<1> IOSTANDARD = LVCMOS25;
Net fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin<2> LOC=AE14;
Net fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin<2> IOSTANDARD = LVCMOS25;
Net fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin<3> LOC=AN12;
Net fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin<3> IOSTANDARD = LVCMOS25;
Net fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin<4> LOC=AM12;
Net fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin<4> IOSTANDARD = LVCMOS25;
Net fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin<5> LOC=AD11;
Net fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin<5> IOSTANDARD = LVCMOS25;
Net fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin<6> LOC=AC12;
Net fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin<6> IOSTANDARD = LVCMOS25;
Net fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin<7> LOC=AC13;
Net fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin<7> IOSTANDARD = LVCMOS25;
Net fpga_0_Hard_Ethernet_MAC_GMII_RX_DV_0_pin LOC=AM13;
Net fpga_0_Hard_Ethernet_MAC_GMII_RX_DV_0_pin IOSTANDARD = LVCMOS25;
Net fpga_0_Hard_Ethernet_MAC_GMII_RX_ER_0_pin LOC=AG12;
Net fpga_0_Hard_Ethernet_MAC_GMII_RX_ER_0_pin IOSTANDARD = LVCMOS25;
Net fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0_pin LOC=AP11;
Net fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0_pin IOSTANDARD = LVCMOS25;
Net fpga_0_Hard_Ethernet_MAC_MII_TX_CLK_0_pin LOC = AD12;
Net fpga_0_Hard_Ethernet_MAC_MII_TX_CLK_0_pin IOSTANDARD = LVCMOS25;
Net fpga_0_Hard_Ethernet_MAC_MDC_0_pin LOC=AP14;
Net fpga_0_Hard_Ethernet_MAC_MDC_0_pin IOSTANDARD = LVCMOS25;
Net fpga_0_Hard_Ethernet_MAC_MDIO_0_pin LOC=AN14;
Net fpga_0_Hard_Ethernet_MAC_MDIO_0_pin IOSTANDARD = LVCMOS25;
###### Hard_Ethernet_MAC
# This is a GMII system
# GTX_CLK_0 = 125MHz
# LlinkTemac0_CLK = plb_v46 clk = host clock = 100MHz from clock generator
# Rx/Tx Client clocks are Rx/Tx PHY clocks so CORE Gen PHY clock constraints propagate to Rx/Tx client clock periods
# Time domain crossing constraints (DATAPATHONLY) are set for maximum bus frequency
# allowed by IP which is the maximum option in BSB. For lower bus frequency choice in BSB,
# the constraints are over constrained. Relaxing them for your system may reduce build time.
net "*/hrst*" TIG;
net "*/V6HARD_SYS.I_TEMAC/speed_vector_0_i*" TIG;
NET "*Hard_Ethernet_MAC*/LlinkTemac0_CLK" TNM_NET = "LLCLK0"; #name of signal connected to TEMAC LlinkTemac0_CLK input
NET "*Hard_Ethernet_MAC*/SPLB_Clk" TNM_NET = "PLBCLK"; #name of signal connected to TEMAC SPLB_Clk input
##################################################
# CLOCK CONSTRAINTS
# The following constraints are required. If you choose to not use the example
# design level of wrapper hierarchy, the net names should be translated to
# match your design.
##################################################
# Ethernet GTX_CLK high quality 125 MHz reference clock
# __________
# -GTX_CLK_0----------| |
# | BUFGCTRL |---Tx_Cl_Clk
# -MII_TX_CLK_0-------|__________|
#
# Changed NET
# NET "GTX_CLK" TNM_NET = "ref_gtx_clk";
# modified by rong
# NET "Hard_Ethernet_MAC*/GTX_CLK_0" TNM_NET = "ref_gtx_clk"; #name of signal connected to TEMAC GTX_CLK_0 input
NET "*Hard_Ethernet_MAC*/GTX_CLK_0" TNM_NET = "ref_gtx_clk"; #name of signal connected to TEMAC GTX_CLK_0 input
TIMEGRP "v6_emac_v1_3_clk_ref_gtx" = "ref_gtx_clk";
TIMESPEC "TS_v6_emac_v1_3_clk_ref_gtx" = PERIOD "v6_emac_v1_3_clk_ref_gtx" 8 ns HIGH 50 %;
# Multiplexed 1 Gbps, 10/100 Mbps output inherits constraint from GTX_CLK
# __________
# -GTX_CLK_0----------| |
# | BUFGCTRL |---Tx_Cl_Clk
# -MII_TX_CLK_0-------|__________|
#
# Changed NET name
# NET "tx_clk" TNM_NET = "ref_mux_clk";
NET "*/Tx_Cl_Clk" TNM_NET = "ref_mux_clk";
TIMEGRP "v6_emac_v1_3_clk_ref_mux" = "ref_mux_clk";
TIMESPEC "TS_v6_emac_v1_3_clk_ref_mux" = PERIOD "v6_emac_v1_3_clk_ref_mux" TS_v6_emac_v1_3_clk_ref_gtx HIGH 50%;
# Ethernet GMII PHY-side receive clock
# __________
# | |
# --- GMII_RX_CLK_0---| BUFR |---RxClientClk_0
# |__________|
#
# Changed NET name
# NET "GMII_RX_CLK" TNM_NET = "phy_clk_rx";
NET "*/RxClientClk_0" TNM_NET = "phy_clk_rx";
TIMEGRP "v6_emac_v1_3_clk_phy_rx" = "phy_clk_rx";
TIMESPEC "TS_v6_emac_v1_3_clk_phy_rx" = PERIOD "v6_emac_v1_3_clk_phy_rx" 7.5 ns HIGH 50 %;
# IDELAYCTRL 200 MHz reference clock
# Changed NET name
# NET "REFCLK" TNM_NET = "clk_ref_clk";
NET "*/REFCLK" TNM_NET = "clk_ref_clk";
TIMEGRP "ref_clk" = "clk_ref_clk";
TIMESPEC "TS_ref_clk" = PERIOD "ref_clk" 5 ns HIGH 50 %;
# Constrain the DCR interface clock to an example frequency of 100 MHz
# Changed NET name
# NET "DCREMACCLK" TNM_NET = "host_clock";
NET "*/SPLB_Clk" TNM_NET = "host_clock";
TIMEGRP "clk_host" = "host_clock";
TIMESPEC "TS_clk_host" = PERIOD "clk_host" 10 ns HIGH 50 %;
##################################################
# PHYSICAL INTERFACE CONSTRAINTS
# The following constraints are necessary for proper operation, and are tuned
# for this example design. They should be modified to suit your design.
##################################################
# GMII physical interface constraints
# --------------------------------------------------
# Set the IDELAY values on the PHY inputs, tuned for this example design.
# These values should be modified to suit your design.
INST "*gmii*ideldv" IDELAY_VALUE = 30;
INST "*gmii*ideld0" IDELAY_VALUE = 25;
INST "*gmii*ideld1" IDELAY_VALUE = 31;
INST "*gmii*ideld2" IDELAY_VALUE = 31;
INST "*gmii*ideld3" IDELAY_VALUE = 27;
INST "*gmii*ideld4" IDELAY_VALUE = 29;
INST "*gmii*ideld5" IDELAY_VALUE = 31;
INST "*gmii*ideld6" IDELAY_VALUE = 31;
INST "*gmii*ideld7" IDELAY_VALUE = 31;
INST "*gmii*ideler" IDELAY_VALUE = 22;
# This signal trace is longer than the clock trace, and arrives at the FPGA pin ~65 ps after the clock
# Therefore the offset in constraint must have less setup time than nominal
NET fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin[0] OFFSET = IN 2.435 ns VALID 3 ns BEFORE "fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0_pin";
# This signal trace is shorter than the clock trace, and arrives at the FPGA pin ~375 ps before the clock
# Therefore the offset in constraint must have more setup time than nominal
NET fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin[1] OFFSET = IN 2.875 ns VALID 3 ns BEFORE "fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0_pin";
# This signal trace is shorter than the clock trace, and arrives at the FPGA pin ~372 ps before the clock
# Therefore the offset in constraint must have more setup time than nominal
NET fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin[2] OFFSET = IN 2.872 ns VALID 3 ns BEFORE "fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0_pin";
# This signal trace is shorter than the clock trace, and arrives at the FPGA pin ~115 ps before the clock
# Therefore the offset in constraint must have more setup time than nominal
NET fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin[3] OFFSET = IN 2.615 ns VALID 3 ns BEFORE "fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0_pin";
# This signal trace is shorter than the clock trace, and arrives at the FPGA pin ~244 ps before the clock
# Therefore the offset in constraint must have more setup time than nominal
NET fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin[4] OFFSET = IN 2.744 ns VALID 3 ns BEFORE "fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0_pin";
# This signal trace is shorter than the clock trace, and arrives at the FPGA pin ~404 ps before the clock
# Therefore the offset in constraint must have more setup time than nominal
NET fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin[5] OFFSET = IN 2.904 ns VALID 3 ns BEFORE "fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0_pin";
# This signal trace is shorter than the clock trace, and arrives at the FPGA pin ~498 ps before the clock
# Therefore the offset in constraint must have more setup time than nominal
NET fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin[6] OFFSET = IN 2.998 ns VALID 3 ns BEFORE "fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0_pin";
# This signal trace is shorter than the clock trace, and arrives at the FPGA pin ~485 ps before the clock
# Therefore the offset in constraint must have more setup time than nominal
NET fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin[7] OFFSET = IN 2.985 ns VALID 3 ns BEFORE "fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0_pin";
# This signal trace is shorter than the clock trace, and arrives at the FPGA pin ~291 ps before the clock
# Therefore the offset in constraint must have more setup time than nominal
NET fpga_0_Hard_Ethernet_MAC_GMII_RX_DV_0_pin OFFSET = IN 2.791 ns VALID 3 ns BEFORE "fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0_pin";
# This signal trace is longer than the clock trace, and arrives at the FPGA pin ~308 ps after the clock
# Therefore the offset in constraint must have less setup time than nominal
NET fpga_0_Hard_Ethernet_MAC_GMII_RX_ER_0_pin OFFSET = IN 2.192 ns VALID 3 ns BEFORE "fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0_pin";
# Constrain the GMII physical interface flip-flops to IOBs
# Changed from 'true' to 'force'
INST "*gmii?RXD_TO_MAC*" IOB = force;
INST "*gmii?RX_DV_TO_MAC" IOB = force;
INST "*gmii?RX_ER_TO_MAC" IOB = force;
INST "*gmii?GMII_TXD_?" IOB = force;
INST "*gmii?GMII_TX_EN" IOB = force;
INST "*gmii?GMII_TX_ER" IOB = force;
TIMESPEC "TS_LL_CLK0_2_RX_CLIENT_CLK0" = FROM LLCLK0 TO phy_clk_rx 8000 ps DATAPATHONLY; #constant value based on Ethernet clock
TIMESPEC "TS_LL_CLK0_2_TX_CLIENT_CLK0" = FROM LLCLK0 TO ref_mux_clk 8000 ps DATAPATHONLY; #constant value based on Ethernet clock
TIMESPEC "TS_RX_CLIENT_CLK0_2_LL_CLK0" = FROM phy_clk_rx TO LLCLK0 10000 ps DATAPATHONLY; #varies based on period of LocalLink clock
TIMESPEC "TS_TX_CLIENT_CLK0_2_LL_CLK0" = FROM ref_mux_clk TO LLCLK0 10000 ps DATAPATHONLY; #varies based on period of LocalLink clock
// UCF FILE done
Re: "WARNING:C
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05-11-2012 06:33 PM
Pls Somebody help me !
I'm stuck at this problem for almost a week.
Re: "WARNING:C
[ Edited ]
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05-12-2012 05:54 AM - edited 05-12-2012 05:55 AM
I'm stuck at this problem for almost a week.
Open a webcase for direct support from Xilinx.
-- Bob Elkind
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369
Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
Re: "WARNING:C
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05-14-2012 05:55 PM
Thanks. I'll do it right now!
Re: "WARNING:C
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12-07-2012 02:27 AM
Hello,
i have the same Problem. Is there any Solution?
Re: "WARNING:C
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12-08-2012 07:06 AM
have a look at this AR http://www.xilinx.com/support/answers/34900.htm .
you will get info to resolve thids issue
Re: "WARNING:C
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01-18-2013 05:42 AM
Hi,
This is caused by duplicate locate constraints (or LOC constraints) being placed in the UCF.
