03-28-2012 09:50 AM
2 weeks ago, i have a design, and the place and route need more less 20 minutes to finish.
in this week, the same design, only need 4 minutes to finish, and the .bit does not work properly.
By the other hand, in my design, there are many blocks, but i reduced it in a ONLY one component. After, i use some blocks of Lyrtech that cointaing vhd, netlist, ucf... that configure the Virtex4. In a vhd file, i insert my component.
The place and route of my (only) design need 10 minutes.
The place and route of the enrtire design (my design+other archives of Virtex4) need only 4 minutes!!!!!!
I don't have any warnings (except IP cores--> black module), i don't have any infos, i don't have any strange information.
03-28-2012 02:15 PM
i don't change anything!!! that is the strange thing.
if i change something, i can undestand that the process os synthetize, implement desing will be change, but the problem is that i have not change anything.
i don't know how the time could be change, if i don't change the code.
thank you for your reply