12-08-2011 08:06 AM
Can anyone point me to where I can find info on how to generate/apply secure IP onto cores? Is there a special tool for this?
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12-08-2011 08:22 AM
Unfortunately we dont have a way to use SecureIP for anything other then simulation right now. There is a project under way to add more to this flow. Please contact Xilinx tech support for more details on this.
For using it with simulation, all the major EDA vendors support the IEEE 1364-2005 encryption standards. This is what we use for delivering the SecureIP models.
12-08-2011 08:30 AM
I was under the impression IP vendors protect their RTL source code with something that has been standardized amongst the major EDA tools. Was this just a good idea that never developed?
12-08-2011 08:37 AM
Yes that is in developement. There is the P1735 IEEE WG driving this initiative. Currently it has not really had a ratified spec as yet and this is what i meant by there are further enhancements being done. The status today is that there is a level of interop (without rights management) between Mentor, Cadence, Aldec and some support in Xilinx tools for Version 1.0.
This is a larger discussion, so I would recomemnd opening a case on this.