MIG (Memory Interface Generator)

[gerard.visser]

Hello,

  Does anybody have experience with a 4Gbit SDRAM run with Spartan-6 MCB? I am in the preliminary stages of design for a project requiring 1 GByte of memory on an FPGA and propose to use two 4Gbit chips, specifically Micron # MT41J256M16RE-125:D with XC6SLX45-3FGG484C. I would be very grateful to hear of any experience with this combination of parts or anything similar. As much detail as you care to share...

  Also:

1. Should I use series or parallel termination on the non-data lines? The eval board uses parallel termination but I understand series termination is also reasonable, and I've used in past (for much slower DDR(1) memory). Of course will use ODT for the data lines. The memory chip will be "as close as reasonable" to the FPGA, probably 0.4 inch edge-to-edge or so.

2. This will always be used with fixed length bursts and correspondingly aligned address. So, I can just tie the UDM, LDM signals asserted to the memory, rather than routing them, right?

3. What memory clock frequency is "best"? The slowest is more than fast enough for the data rates of this application (400 MBytes/s total memory I/O).

4. The system clock source would be a lower-frequency oscillator (likely 80 MHz), can this be single-ended? Of course will be located right next to the FPGA and routed nicely.

Sincerely,

    Gerard Visser

p.s. FYI I am an experienced designer with many FPGA's done including several Spartan-6. But I don't have much experience with SDRAM, and none with DDR3...

[eteam00]

Running MIG 3.91, and selecting create custom part", it seems that the Spartan-6 MCB supports up to

• 15 row address bits
• 12 column address bits
• 3 bank address bits

These limits rule out 512Mx8 and 1Gx5 devices, but would support 256Mx16 devices -- including the MT41J256M16RE.

In MIG, select "create custom part" using MT41J128M16xx-125 as a base part (because it has similar timing specs and data width).  Select

• 15 row address bits
• 10 column address bits
• 3 bank address bits

-- Bob Elkind

[gerard.visser]

Hi Bob,

   Thank you for the reply on that. Yes although I didn't do this "custom part" definition yet, I had already received similar advice. I am really sorry that I failed to mention it in my original post.

  But has anyone reading here actually run the 4Gbit part with Spartan-6? I am simply a bit nervous to commence an expensive board design effort when all the available reference designs use 1Gbit. As a DDR3 novice I am nervous that I'm missing something here. I needn't add that the memory chip datasheets are quite complex and I don't think I can determine from that approach if the 1Gbit and 4 Gbit use identical protocols/timing.

  Also, do you have any advice on the 4 numbered questions, it would be much appreciated.

  Thanks in advance,

    Gerard

[eteam00 · Accepted solution]

But has anyone reading here actually run the 4Gbit part with Spartan-6? I am simply a bit nervous to commence an expensive board design effort when all the available reference designs use 1Gbit.

Very understandable, from your position.  Generally speaking, if you can successfully synthesise and simulate your design with Xilinx and Micron models, Xilinx should stand behind the results.  This would be reassuring to you and your project colleagues.  If you have further concerns or problems, suggest you open a webcase, and obtain direct guidance from Xilinx insiders. 

1. Should I use series or parallel termination on the non-data lines? The eval board uses parallel termination but I understand series termination is also reasonable, and I've used in past (for much slower DDR(1) memory). Of course will use ODT for the data lines. The memory chip will be "as close as reasonable" to the FPGA, probably 0.4 inch edge-to-edge or so.

With the address/control group signals, which is unidirectional and point-to-point connection, you should be able to use series termination, with the termination resistance provided by the FPGA output drivers.  Here are your 'risk options', in ascending order:

• lowest risk:  parallel termination using the Xilinx MIG application docs as your guide.
• somewhat higher risk:  series termination, with external Rs on the board (nominally 0 ohm, as they are likely not needed)
• greater risk (but still low, IMHO):  series termination, with series R provided by intrinsic impedance of S6 output buffers, plus internal output termination.

If you opt for a series termination scheme, the Spartan-6 output driver impedance must be considered.  In Spartan-6 family there is only one DDR3-friendly drive level and IOSTANDARD selection:  SSTL15_II.  You can add additional series impedance with the output termination options (See DS162 Table 4, ROUT_TERM).  The buffer and output termination impedance is not a tight tolerance spec, it can vary from nominal by -50% - +100%.  Whatever you select for output termination, plus the intrinsic impedance of the S6 output buffer, will be added to the effective value of external series termination Rs (if you choose to use them).

Unlike clocks and strobes and DQ lines, in the case of the address/control group signals there is no risk whatsoever that the interface will not work because of the series termination topology.  The risk is reduced performance (operating frequency), and nothing more.

As Austin Lesea would say, analogue circuit simulation (using the Xilinx and Micron IBIS models) should help your comfort level.

2. This will always be used with fixed length bursts and correspondingly aligned address. So, I can just tie the UDM, LDM signals asserted to the memory, rather than routing them, right?

To permit data WRITE, the DM signal must be LOW (or de-asserted).  The optimisation you describe seems logical, but the payback is very low -- only two pin connections on the FPGA (per DRAM).  I would suggest doing this only if you are desperate.

3. What memory clock frequency is "best"? The slowest is more than fast enough for the data rates of this application (400 MBytes/s total memory I/O).

Designer discretion.  See what your peak memory bandwidth requirements are, and scale the operating frequency appropriately.  This is primarily a 'soft' adjust, easily updated in FPGA firmware, if you generate the memory and system clocks from a low-frequency input clock (e.g. 80 MHz).

The power consumed by DDR3 DRAMS is mostly dynamic.  In other words, you (generally) burn the same power for each access, whether the access is with a higher or lower frequency clock.  Even if you do not save much power, using a lower-frequency clock means that timing margins are greater, an important consideration.

4. The system clock source would be a lower-frequency oscillator (likely 80 MHz), can this be single-ended? Of course will be located right next to the FPGA and routed nicely.

Yes, single-ended is fine.  Use a 33-ohm series temination resistor, even if the trace length is short.

-- Bob Elkind

[juergenatduerr]

"33 Ohm series termination"

would you consider this for all mcb designs using single ended clocks?

[eteam00]

"33 Ohm series termination"

would you consider this for all mcb designs using single ended clocks?

The context for this recommendation is an external oscillator clock source, and is not associated with Spartan-6 MCB.

I'll re-phrase your question in the following answer:

A 33-ohm series termination resistor is a good idea for all circuit board designs using single-ended clock generators, assuming a single-source single-load connection.

This advice is offered as a rule-of-thumb for simple TTL/CMOS clock connections (single source, single load, single-ended). It's a generalisation and a simplification, and it almost always works well.

You can identify circumstances in which this is not an optimal design, but in such circumstances the circuit can be made optimal by simply changing the series termination resistor value (adjusting it higher or lower, or even to zero).

On the other hand, designs which need the series R and don't provide it will usually end up requiring an expensive and time-consuming circuit board revision.

-- Bob Elkind