06-05-2012 07:48 AM - edited 06-05-2012 07:50 AM
Has anybody been successful with simulating the example design that is generated with Core Generator 13.4 when we create a MIG AXI design?
I first run the script mig_7series_v1_4\example_design\sim\isim_run.bat and none the AXI Signals were moving. I opened a thread at the time, you can read it here.
Then, after doing some more research by myself, I found that the reference design came with a .pdf with known issues and the ways to solve them.
Good! That allowed me to perform the changes in the attachment file. This resulted in me being able to see calibration being complete on the board.
Unfortunately, I still can't access the DDR3, and so I am in need to see the verilog text fixture working. However, even after the corrected issues, the simulation does not work. The AXI Signals never move and the DDR3 does not even calibrate.
Anybody facing the same problems?