Both MIG and clock gen wizard have been told (or assume) an external (package pin) source for the clock. Both core generators are inferring input buffers. When you connect MIG and clock gen signal ports together, then XST sees cascaded (series) input buffers.
In the MIG-generated source code, follow the input clock port signal through the wrapper code to the infrastructure.v code, and edit the infrastructure.v file to remove the redundant buffer.
You are clearly using either Virtex-5 or Virtex-6 device. In such posts as yours, the identity of the target device family is essential information. For core generators such as MIG, output is very different for each device family.
... it synthesize successfully, but when I translate the design, it produce this Error message...
Please explain, what is the difference between 'synthesize' and 'translate' in your post? I consider 'translate' to be part of the 'synthesis' process, rather than two different processes.
Is there a reason you are not using ISE 12.4 or 13.4 instead of 12.1?
-- Bob Elkind
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