MIG (Memory Interface Generator)

[james.o.clay@lmco.com]

I have a Spartan 6 LX150 FPGA, and would like to use a 1Gb LPDDR DRAM.  It is an embedded system, though, so minimizing power consumption is crucial.

I will use the DRAM occasionally, but only a small percentage of the time, so I would like to be able to power down the DRAM when I'm not using it and, if possible, the MCB as well.  I have done searches and read a fair amount of the literature and I don't see anything that says that this is possible, other than suspending the whole FPGA which I cannot do.  Is there any solution?  I don't care about preserving the DRAM's data when I power it down.

[gszakacs]

You could just assert the MIG reset input when you want to save power.  The down side to this is

that you'll need to wait for calibration to complete every time you start it back up.

-- Gabor

[vsrunga]

Hi,

For deatils on waht gabot say you may look in to http://www.xilinx.com/support/documentation/user_guides/ug388.pdf  suspend section from pg 59 onwards

Regards,

[james.o.clay@lmco.com]

Thank you both for your responses.  I apologize for my delay in responding- I was out on Monday and Tuesday.

Asserting reset seems like a workable solution.  The documentation is not clear on what happens when you do it though.  Does it set the DRAM clock enable low and the chip select high?  I assume it doesn't put the DRAM into "deep power down" mode.  Is this right?

[eteam00]

Reset to the MCB will cause clocks to the memory to stop.  DRAM contents will be lost.  Check the DRAM datasheet for power consumption level with no refreshes and no accesses.

-- Bob Elkind

[james.o.clay@lmco.com]

Bob,

Thanks for the information.  Do you know if it sets the clock enable low and chip select high as well, or do those lines go high-impedance?

[eteam00 · Accepted solution]

Do you know if it sets the clock enable low and chip select high as well, or do those lines go high-impedance?

Clock enable is part of the Spartan-6 controller interface to the memory, but chip select is not.  You can (and must) explicitly control chip select if it is connected to the FPGA.

-- Bob Elkind