03-04-2010 05:06 PM
I am trying to figure out if the DDR3 controller that MIG produce can support continuous read burst. From ug406 figure 1-81, the data valid is only active for six clocks. Hence, there is not enough time shown to know if this controller can support continuous read burst.
Furthermore, from figure 1-82, the 00 on dq_fpga that presents for 1 full clock cycle seems suspicious. It is as it is doing cyclic burst instead of continuous burst.
Could anybody confirm if the MIG support continuous read burst?
03-05-2010 11:13 AM
03-08-2010 02:55 PM
The sentence was missing cyclic. it is supposed to be continuous cyclic read.
It appears that on DDR3 both read and write are burst mode only.
So could you point out on a document that shows the support for cont read burst?
Furthermore, can the DDR3 controller produced by the MIG drive 4 paralleled SODIMMs? Or do we have to create different controllers for each modules?
03-09-2010 07:28 PM
I'm not aware of a document showing the continuous read burst. I can ask that something be put in for a release in the future.
MIG does not allow 4 slots in parallel. You'll need a controller for each SODIMM. It is possible use 2 SODIMM's for a wide interface of 128 bits. However, the operating frequency is limited in this case. Source is given out by MIG so you can modify the controller as you wish.