MIG (Memory Interface Generator)

[jjonathan]

Hello,

I am trying to figure out if the DDR3 controller that MIG produce can support continuous read burst. From ug406 figure 1-81, the data valid is only active for six clocks. Hence, there is not enough time shown to know if this controller can support continuous read burst.

Furthermore, from figure 1-82, the 00 on dq_fpga that presents for 1 full clock cycle seems suspicious. It is as it is doing cyclic burst instead of continuous burst.

Could anybody confirm if the MIG support continuous read burst?

Thanks

[jschmitz]

As long as you keep the request queue full of reads to a row (modulo refresh and ZQ calibration), the controller will read continuously.  Same for writing.  If you have gaps in your requests, the default mode of the controller will close the page.

[jjonathan]

Is there a document that shows that the MIG is capable of doing continuous burst read? Please note that this is different than continuous read.

thanks

[jschmitz]

Can you clarify what you mean by "continuous burst read" versus "continuous read"?

[jjonathan]

The sentence was missing cyclic. it is supposed to be continuous cyclic read.

It appears that on DDR3 both read and write are burst mode only.

So could you point out on a document that  shows the support for cont read burst?

Furthermore, can the DDR3 controller produced by the MIG drive 4 paralleled SODIMMs? Or do we have to create different controllers for each modules?

Thanks

[jschmitz]

I'm not aware of a document showing the continuous read burst.  I can ask that something be put in for a release in the future.

MIG does not allow 4 slots in parallel.  You'll need a controller for each SODIMM.  It is possible use 2 SODIMM's for a wide interface of 128 bits.  However, the operating frequency is limited in this case.  Source is given out by MIG so you can modify the controller as you wish.