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Visitor
chaoloveai120
Posts: 4
Registered: ‎03-31-2012
0

DDR SDRAM using MIG implemented on spartan 3E starter board problem

I'm  a beginer to FPGA , Now I generated  the DDR SDRAM  reference design with MIG Tool (ISE 13.1). I added  the example design RTL  and ucf  to my  ISE and modified the UCF which meets spartan 3E starter board . Buf after synthesize and implement , Only one timing wasn't  meeted, and the init done led is turned on(which implies  init is OK ),the error led is turned on(which implies  timing is not meeted ),the data_valid led is turned on (which implies  data valid is OK)

I tried a lot of methods to solve the problem,but it didn't work .  Could anyone give me a hand. The design is as below. which including all of the files .

Visitor
chaoloveai120
Posts: 4
Registered: ‎03-31-2012
0

Re: DDR SDRAM using MIG implemented on spartan 3E starter board problem

 
Expert Contributor
eteam00
Posts: 7,505
Registered: ‎07-21-2009
0

Re: DDR SDRAM using MIG implemented on spartan 3E starter board problem

[ Edited ]

It is difficult and time-consuming to answer a problem such as "here is my design, it doesn't work, please debug it for me".

 

Please try to narrow the focus of your problem.  'This LED stays lit' is not an informative problem description.

Try to understand how your design works, and the possible causes for certain events (for example, "the error led is turned on").

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
Visitor
chaoloveai120
Posts: 4
Registered: ‎03-31-2012
0

Re: DDR SDRAM using MIG implemented on spartan 3E starter board problem

Thank you for your reply.  But I wonder  that  we can't  use  MIG methods implement DDR SDRAM at high frequency(for example 100M and above )  on  the spartan 3E  starter kit  .  Because the  UCF of this kit is fixed . And we can't  spare extra IO (in bank 3)for rst_dqs_div_in or rst_dqs_div_out  or just rst_dqs_div signal . So I think that's a drawback of the Spartan 3E starter kit . and that's why DDR SDRAM  implemented through Microblace . But the  Spartan 3A starter kit  implement the DDR or DDR2 powerful through MIG.

 

 

So  I wish xilinx engineers and other engineers can give me right answer. 

Visitor
juergenfpgaiosb2013
Posts: 3
Registered: ‎03-04-2013
0

Re: DDR SDRAM using MIG implemented on spartan 3E starter board problem

Hi,

 

I have the same issue. I did not get the DDR controller to work. Has anybody  an working example? I am trying about two weeks without any success.

 

Thanks for help.

 

Jürgen

Newbie
tanyonglak
Posts: 1
Registered: ‎05-06-2013
0

Re: DDR SDRAM using MIG implemented on spartan 3E starter board problem

Hi Jurgen,

 

You won't find much help here despite several people had posted similar difficulties with DDR on starter board for some years.

Forget about MIG if you only want to get some usefulness out of the DDR. The most unlikely places to get help

on the starter kit. I wished I've known this site much sooner. The DDR 'Hello World' example is what you're looking

for as it works on my 1600e board.

 

http://electro-music.com/forum/topic-49909.html

http://jovianpyx.dyndns.org:8080/public/FPGA_synth/SDRAM_hello_world.zip

 

regards

lak