MIG (Memory Interface Generator)

[luyang81]

We are going to design a product with large/fast memory buffer, we plan to use Kintex7 XC7K70T in the new design, and we plan to implement three 16bit DDR3 memories on board, but XC7K70T only have two HP banks. Is it possible to use do 48bit (3x16bit) DDR3/1600 in two banks? Thanks a lot!

[jschmitz]

Are you asking for 3 independent controllers in two banks?  This is not possible.

If you are asking for a single 48 bit controller in 2 banks, the answer is possibly.  You may need to use every trick in the book.  Also, it depends on the memory density.  Tricks include: DCI cascade, no data mask, no CS pin, no ODT pin.  You may need to drive the reset pin to the memory from another bank through a level shifter.  The clock must come into these banks.  With lower density memory parts, it is easier.

Take a look at the 'DDR3 Pinout Examples' in the UG586 user guide:

http://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v1_5/ug586_7Series_MIS.pdf

The 16 bit design in one bank is basically the starting point.  Add 4 byte lanes in the adjacent bank, and you get 48 bits in 2 banks.

[luyang81]

We plan to use 1Gb 16bit memory as the basic memory cell and We will use a single 48 bit controller in 2 banks. I have already read the app note you mentioned and I find it may be possilbe to do a single 48 bit controller in 2 banks. But I am not sure whether there are any other limitations or issues in the implementation.

You mentioned that "You may need to drive the reset pin to the memory from another bank through a level shifter. ", will it be supported by the MIG IP?

Thank you very much!

[jschmitz]

The MIG IP will have no idea what you are doing externally to the reset pin.  As long as you hook it up correctly and use a proper level shifter, it should be fine.  You will want to make sure it meets timing.  But you may not need to do this.  Just run MIG with your selections and you should be able to make it fit.  1 Gb x16 parts will help.  As I mentioned, take a look at the pin out examples.  I think you'll find the x16 interface width design is directly applicable to your needs.  Just add one more bank with 4 data byte lanes.

[luyang81]

Hi jschmitz,

Thanks a lot!

[luyang81]

Hi jschmitz,

I am starting to implement the 48bit (3x16bit) controller in  Kintex7 XC7K70T two HP banks. When I use MIG for 7 series to generate the controller, I found the MIG give me a "!" on 48bit with 1600 DDR3 and I can not  go any further. the GUI warning is copied here, can anyone help to solve this issue? Thank you very much!

[jschmitz]

I think you've uncovered a bug in the GUI.  It should allow this, but it doesn't.

Here's a workaround: select the 160T instead.  Do not select the 70T as a compatible part, choose the 1G x16 part, turn off the DM option, turn off the CS pin.  Then go to the bank selection screen.  Use only the banks that are present in the 70T.  At first it will seem that you need 3 byte lanes for address, but you don't.  Put 2 data bytes in the top half of a bank.  Put the first 2 address bytes in the lower half.  Then fill in the remaining 4 data bytes in the adjacent bank.

I think that will work.  You'll then need to adjust the output to target the 70T, but I think the pins should be the same.  Some manual intervention may be required.

You could open a webcase for support on this.