06-08-2012 01:07 AM
I have created a DDR3 core using MIG and the translate and map stages produce the following warning:
WARNING:Pack:2143 - The function generator
].bank0/bank_state0/rtc3". There are more than two MUXF7 wide function
The design will exhibit suboptimal timing.
Has anyone seen this before? Would you be able to help me understand what I might be doing wrong here?
Thanks and Regards,
06-08-2012 01:12 AM
MIG will generate very different controller designs for each of the different FPGA device families.
- What device family are you targeting?
- What revision of MIG (or ISE) are you using?
-- Bob Elkind
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
06-08-2012 06:29 AM
This sort of warning is quite common, and usually you can ignore it if your
design meets timing. Just make sure that the path being mentioned in
the warnings is properly constrained.