DDR3 Core - sub optimal timing warning

cesanka · ‎01-28-2008

Hi,

I have created a DDR3 core using MIG and the translate and map stages produce the following warning:

WARNING:Pack:2143 - The function generator
   "ddr3combinedBankFIFO_1/banks[0].rep_false.Bank0/MEM/MEM_FETOP0_14R_7CL_GEN.MEM/XST_GND" failed to merge with F7 multiplexer
   "ddr3combinedBankFIFO_1/banks[0].rep_false.Bank0/MEM/MEM_FETOP0_14R_7CL_GEN.M
   EM/xilinxWrapperInst/XIL_DDR3_IF/u_mem_intfc/mc0/bank_mach0/bank_cntrl_inst[0
   ].bank0/bank_state0/rtc3". There are more than two MUXF7 wide function
   muxes.
     The design will exhibit suboptimal timing.

Has anyone seen this before? Would you be able to help me understand what I might be doing wrong here?

Thanks and Regards,

Sanka.

eteam00 · ‎07-21-2009

MIG will generate very different controller designs for each of the different FPGA device families.

What device family are you targeting?
What revision of MIG (or ISE) are you using?

-- Bob Elkind

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